Morphology Based Illumination Normalization Research Algorithm And Implementation Of Text Image

The development of OCR technology is spawning a massive text image processing requirements. And in addition to professional special applications, the text image is often obtained by photographing pictures, while photographing would unavoidably lead to uneven illumination. So it’s essential to eliminate the uneven illumination with illumination normalization algorithm before image identification.There exists some commonly used illumination normalization algorithm such as histogram modification, homomorphic filter, Retinex enhancement and morphological algorithm, etc. In the aspect of text image illumination normalization, more or less, there has some shortcomings. The paper describes a kind of top-hat transform based algorithm, with which to extract uneven illumination of the image, and then obtain the illumination normalization text image. The algorithm involves multi-direction structure elements morphology, morphological opening and closing reconstruction technology, top-hat transform, entropy based image fusion technology, morphological contrast enhancement, etc. Algorithm contains the following processes: using open reconstruction instead of open, to redefine top-hat transform in order to prevent generating contour or block effect; increasing close reconstruction operation, to solve the "over-illumination equalization" effect; defining multi-directions structural elements, to match the different direction characteristics, and to obtain subgraphs containing direction information; multi-direction subgraphs are merged to the final even illumination image; using simple morphological contrast enhancement algorithm, to promote contrast enhancement of image.The performance of the proposed algorithm is illustrated and verified through the processing of different ideal synthetic with different illumination model and camera collected images with different text texture. Hardware implementation and the system framework of the algorithm are completed. Block diagram of each function module and related simulation sequence diagrams are also illustrated. And the hardware implementation of the algorithm is functionally verified by using FPGA platform. Finally, the related VLSI layout design is finished.