VLSI Design For2-D Barcode Based Illumination Equalization

Barcode technology, especially the two-dimensional bar code technology, iswidely used in all aspects of daily life due to its large storage capacity, low cost andfault tolerance. Digital image based2-D bar code decoding process has very high imagepre-processing requirements. However, common portable2-D barcode decoder are allbased on the design of general-purpose processor like ARM and DSP, and due to theconstraints of the processing power of image preprocessing, the key step of illuminationbalancing is hard to implement. In nowadays, there is no specific illuminationequalization algorithm for two-dimensional bar code image.Illumination equalization algorithm is a common image processing method forpattern recognition, artificial intelligence, etc. After years of development, the commonIllumination equalization algorithms include Retinex algorithm, histogram equalizationalgorithm, lighting-reflection model algorithm, gradient field enhancement algorithms,etc. This kind of algorithms cost large amount of computation and they are verycomplex. With the development of mathematical morphology, illumination equalizationalgorithm has new solutions. Mathematical morphology is born in1960s and itspecialize in image analysis and processing. The key to mathematical morphology is touse structuring element to process the similar structures in digital images. Mathematicalmorphology gives a rapid development for illumination equalization and imageextraction. In this paper, a mathematical morphology based illumination equalizationalgorithm is proposed, it uses multi-structure elements to perform TOP-HATtransformation, and it can effectively erase the influence of illumination whileprotecting image details.The proposed algorithm involves great sums of computation, so general processoris not suitable to implement this algorithm. In this paper, a VLSI architecture isproposed to implement this algorithm. Using hardware can greatly increase theprocessing speed. This architecture is verified on FPGA board, and it is synthesizedusing SMIC0.13um CMOS process.