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VLSI Design For2-D Barcode Based Image Segmentation

Posted on:2014-10-27Degree:MasterType:Thesis
Country:ChinaCandidate:Y ChenFull Text:PDF
GTID:2268330401965323Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
In the field of computer vision processing, the digital image can be divided intoseveral parts. There are a wide range of applications for image segmentation, includingmedical image processing, satellite image processing, retina recognition, barcodeidentification, traffic control, etc. In nowadays,2-D barcode is widely used in life. Onevery occasion for barcode identification, image pre-processing is a must. Imagesegmentation is a key step for image pre-processing, it can extract barcode out of thecomplex background and greatly improve barcode identification rate.There are many existing image segmentation algorithm, including threshholdsegmentation, cluster segmentation, compression based image segmentation, histogrambased segmentation, edge detection segmentation, region growing segmentation,watershed segmentation, multi-scale segmentation and mathematical morphology basedsegmentation.Mathematical morphology is based on set theory, topology and probability theory,and it can analyse and process digital image very well. In recent years, it is becomingvery popular to process digital image using mathematical morphology, in this paper, thedisadvantages and advantages of several image segmentation algorithms aresummarized, and a mathematical morphology based image segmentation algorithm isproposed to extract barcode image.However, mathematical morphology based image segmentation algorithm canachieve a good processing result, but it is complicated and needs great sums ofcomputation. When implement it using software, the processing speed is slow. In orderto meet the demand of real-time image processing, the VLSI architecture for imagesegmentation is proposed. Hardware architecture can process image concurrently, sothat the processing speed is greatly increased. The VLSI architecture is implementedusing Verilog HDL, and it is verified on FPGA board. At last, this design is synthesizedusing SMIC0.13um CMOS process.
Keywords/Search Tags:Mathematical morphology, image segmentation, VLSI, FPGA
PDF Full Text Request
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