Research Of The Fault-Tolerant Algorithm Of Asynchronous Three-Dimensional Network-on-Chip

With the development of integrated circuit manufacturing process, traditional system on chip based on shared bus architecture can not solve the complex and diverse communication needs, such as interconnect delay, global synchronization and system design efficiency. To solve the bottleneck problem of System on Chip, borrowed from computer networks and parallel computing technology, proposed a new interconnection structure-Network on Chip. It has better scalability, predictability and performance. However, to address the limitations of two-dimensional Network on Chip layout, three-dimensional integration technology combine with Network-on-Chip to a three-dimensional Network-on-Chip architecture to further improve system performance. Meanwhile, added the asynchronous circuit design concept to Network-on-Chip proposed asynchronous Network-on-Chip architecture. It is a good solution to the area and power consumption problem caused by design the huge synchronous Network-on-Chip clock tree. Asynchronous communication between nodes in the network is controlled by the handshake protocol and unified interface. Thus it reduces power consumption and electromagnetic interference, increases reliability, improves the overall performance and meet the needs of high-bandwidth on-chip network.The innovation point of this thesis is as follows:(1) This article proposes a novel low overhead and high efficient fault-tolerant algorithm-a deflection routing methods based on dynamic priority. First, we consider the positional relationship of the current node and the destination proposed DPDR algorithm, bypassing the failure area by deflecting, always choose the best path to transmit data packets; Then, take a two-stage crossbar switch structure router can significant reduction the average delay of packet transmission; Finally, combination this two to get a complete set of fault-tolerance methods. The method can effectively reduce power consumption and average delay, and the area does not increase with the size of the network increases, improving overall performance.(2) Using asynchronous circuit and fault-tolerant routing mechanism, we proposed an asynchronous and fault-tolerant NoC router. Using the four-phase handshake protocol and 1-of-4 encoding, and route calculation units is fault-tolerant hardware design based on the relative position of the current node and the destination node, to choose the path of least hops goal of routing packets bypass the problem area. This design has good scalability and fault-tolerance capability, and is suitable for large-scale global asynchronous local synchronization system.