Implementation Research Of Adaptive Echo Cancellation Based On FPGA

In electronic system, if the receiving antenna and transmitting antenna working at the same time, the energy of the signal, which radiated by transmitting antenna, will be part of reflected back to the receiving antenna, that is called echo interference. Echo interference will reduce the SINR(Signal to Interference and Noise Rate) performance, thereby affect the performance of the system. In severe case, it may cause the system to self-excitation. Aiming at this problem, an adaptive echo interference cancellation system implemented on FPGA is studied in this dissertation.In this system, the input signal is channelized to 16 sub-channel, while at least 3 of them working at the same time. The echo interference is suppressed by adaptive filter algorithm in each sub-channel. The echo return loss enhancement(ERLE) can reach more than 14 dB, which greatly increased the degree of isolation between transmitting antenna and receiving antenna.Firstly, through the Matlab simulation and the calculation of the complexity, three kinds of adaptive filtering algorithm are compared in this dissertation, which are LMS algorithm, AP algorithm and RLS algorithm. Among them, the complexity of LMS algorithm is the lowest one, while the convergence properties can meet the system requirements. Finally the DLMS algorithm is selected to suppress the echo interference of the system, which is suitable for FPGA implementation.Then, the hardware design of echo interference cancellation system is introduced, which supply a simple system environment for the echo cancellation. Based on the existed hardware, the data processing of the front stage and next stage and the control of related hardware are described. In addition, an integer loop delay estimation method is introduced in this dissertation, so that the echo signal and the estimate signal can be aligned in the time domain.The implementation of DLMS algorithm is the focus of this dissertation. The implementation details of each sub-module, including filtering module and updating module, are all described. By adjusting the place & route and reducing the fanout, the working frequency of the design of DLMS algorithm achieves faster than 200 MHz.A joint simulation of Simulink and Modelsim is also introduced in this dissertation. This joint simulation is convenient to change the simulation conditions. Through this joint simulation, it is proved that the logic of the FPGA code can meet the expected requirements.Finally, the FPGA code is downloaded to the hardware to test the correction of this design. The test data is collected by the chipscope software, then calculated in Matlab. The result shows that this design can meet the system requirements.