Fpga-based Adaptive Filter Design In The Echo Cancellation In The Study

The problem of echo cancellation in telecommunication system is researched in this paper by participating the design of voice scheduling system in shooting range photoelectric control area against the background of ASK reconstruction project.An appropriate LMS(Least Mean Square) algorithm of self-adaptive echo cancellation is selected by deep research and analysis of self-adaptive filtering algorithm. Based on the results, other LMS algorithm is carefully researched and an improved variable step-size block LMS algorithm is proposed.FPGA(Filed Programmable Gate Array) of Altera is adopted instead of TI DSP(Digital Signal Processor) for the self-adaptive algorithm realization. By using amounts of hardware multiplication circuits in FPGA, higher speed and real time self-adaptive filtering is designed. LMS, NLMS(Normalized LMS) and DNLMS(Decorrelate Normalized LMS) algorithms are realized by DSP Builder when self-adaptive filtering is carried out by FPGA. By the premise of no influence on the filtering speed and reduction of hardware consumption, DSP Builder and embedded soft core NIOS II are adopted to realize the self-filtering. FPGA circuit with the core component of EP3C25Q240 of cyclone III and Language processing circuit with the core component of TLV320AIC32B are designed.It is practical and ideal choice to realize self-adaptive filtering and echo cancellation in FPGA by circuit simulation and practical circuit debugging.