The Design Of If And Baseband In Transceiver Based On FPGA

This paper combines knowledge of the basic communication principles to introduce the implementation process of IF and baseband in transceiver. The method used is typical and practicality, but without losing the innovation. In this paper, a Cyclone III FPGA is used as the core processor. The system as a whole uses QPSK modulation and demodulation. The transmitter achieves deserialize, symbol mapping, and baseband shaping filter algorithms. The receiver achieves carrier synchronization, symbol synchronization, frame synchronization and anyother core algorithms.Due to the modular design requirements and the characteristics of each program, the author chose the typical superheterodyne structure as the hardware design at last. The author adopts orthogonal frequency converters made by Analog Device Inc. as the analog modulator and demodulator. The TxDAC and RxADC are customized data converters used by communication system. In addition, this paper has described the driver software design of oscillator clock source(fractional PLL), making the local oscillator frequency of IF and RF easy to be fine adjusted in steps of 50 KHz.The transmitter scrambles the input data first and then executes constellation mapping in accordance with QPSK. The pulse shaping filter is a root raised cosine FIR filter, which is implemented by FPGA.For the receiver, the focus is synchronization. After studying the costas loop and the hardware circuit, the author adopted a feedback compensation method to implement carrier synchronization. In addition, this article has been innovative in the realization of the symbol synchronization algorithm. The algorithm is called integral early-late gate based on a feedback loop. Carrier synchronization and symbol synchronization have a similar feedback loop implementation structure. Experiments show that the carrier synchronization and symbol synchronization algorithm are feasible, and have a good performance.The author adopts a "top-down" design idea, which means that the complex system is divided into underlying single functional modules, and these single modules are then described by Verilog HDL language one by one. FPGA has a strong real-time and parallel processing capability, making it easy to meet the needs of communication systems.The final achievement of this paper is the realization of the communication at 140 MHz in IF, and the wireless communication at 2.45 GHz in RF through using the RF front-end modules. The baseband in the paper has a symbol rate of 1M symbol/s and a data transfer rate of 2M bps. To facilitate testing, the author designs an external communication interface for data exchange. This interface which has data caching capabilities provides a way for the upper host(such as PCs and MCUs) to inject source datas into transceiver, and enhances the practicability at the same time.