Design Of Shallow Trench DMOS

In recent years, the development of communication and automation industries are constantly pulling the demand for power devices, and with the constant development of semiconductor manufacturing technology, the production cost of power devices, performance and size have been greatly improved, its field of application is broad. Compared to the traditional Trench gate planar DMOS device type device has a lower on-resistance, but it is more complex in manufacturing process, our country in this field is still relatively weak ability to independently design, the main core technologies are mastered by foreign companies, the market on most similar products go through foreign imports. This paper designed a shallow trench gate DMOS device has a lower on-resistance and a wider safe operating area, which has a great value.In this thesis, the main work is:First of all, introduced the main electrical parameters P-channel shallow trench gate DMOS devices and gives the corresponding physical model that provides a theoretical basis for the subsequent design process, and on this basis a simulation optimization. Comparing different cell structure and judge pros and cons.On the base of analysis, preliminary determine the parameters of cell, and according to mature manufacture condition to propose a process flow. Use simulation software MEDICI to optimize to reach the index.Finally use the optimized cell parameters to different cell design and compare the tape out results to pick out the best, and which turn out to meet initial requirement: reverse voltage of-38 V,-2.8V threshold voltage and on-resistance of 0.56 ?.