Optimization Method Of GPS/BD2Dual-mode Baseband Signal Processing Based On FPGA

Now the global satellite navigation system-GNSS (Global Navigation Satellite System) is widely used in many fields, the developed countries and regions in the world have put forward their own satellite navigation systems. GNSS receiver is developing from the past single GPS mode to the multimode. Compared to single mode GNSS receiver, multimode GNSS receiver is better in stability, navigation accuracy, security, integrity, than the single mode one, which is currently a hot topic in this field. In China, with the commercial application of BD2GNSS system, research on multi-mode GNSS receiver of GPS and BD2has wide application and a very good market prospect. In this paper, baseband signal processing approaches of the dual-mode GNSS receiver, which is the core of the receiver, is addressed.Firstly, the existing satellite navigation systems are summarized. The basic principles and signal structure of GPS, BD2satellite navigation system are described in detail. The same processing algorithms are adopted in baseband signal of GPS and BD2in the design of the dual mode system of the receiver, because of the similarity of GPS and BD2navigation system’s signal structure.For the acquisition part of baseband signal processing, this paper briefly introduces the time-domain sliding correlation and parallel code phase search algorithm, and an improved time domain search algorithm is proposed.The acquisition speed is improved by optimizating the the acquisition algorithm. The simulation has been carried out with Matlab, the dataset is from an actual sampling IF signal, the correctness of the proposed algorithm is verified.For the tracking part of baseband signal processing, the error of the phase discriminator is analyzed, and a polynomial approximation of arctan function calculation is proposed, which reduces the computation complexity greatly. The carrier tracking loop is optimized in the tracking loop. Delay locking loop is employed for the code tracking loop.A verification platform based on FPGA+ARM is introduced. Based on this platform, the structure of the dual-mode receiver is designed. The modules required by a single channel are designed with VHDL language, which are integrated together, and behavior simulations of these modules are conducted in Modelsim.