Design Of Fpga-Based Multi-Channel Video Combining And Enhancement Processing Algorithms

Video surveillance technology has been widely used in security, transportation, aviation and other fields. Multi-channel video combining and enhancing technology is a basic processing technology in video surveillance, and is directly related to work of video surveillance system. Since traditional video processing methods are unable to meet the real-time of multi-channel video processing system, the processing method of FPGA-based multi-channel video is presented. Because of the FPGA’s hardware parallism, the real-time processing performance of multi-channel video is entirely achieved. So the design of FPGA-based multi-channel video combining and enhancement processing algorithms has important practical significance.The characteristics of the digital video signal and the basic structure of FPGA are presented. Because FPGA is suitable for the large-data operation and the structure of parallel algortithm, the thesis designs FPGA-based multi-channel video combining and enhancing methods. Works and achivememts are presented as follows.(1) The BT.656video data protocol is analyzed, the FPGA-based video processing technology is presented and the FPGA parallel processing and caching technology is elaborated in video processing system.(2) The thesis designes concrete realization scheme that four-channel CIF video is conbined to one-channel Dl video. The all modules of FPGA are designed, they contain enter detection module, asynchronous FIFO, super-frame detection module, DDR2controller, the control module of video read and write, BT.656coding module. The design is verified on the hardware platform, and the FPGA resource utilization and power consumption of the design are also analyzed.(3) The image enhancement of the conbined D1video is realized on FPGA. Comparative analysis of variety video image filtering algorithm is implemented, and a good retention property of the image detail is demonstrated for the Multilevel Median Filtering algorithm. The logic structure of the Multilevel Median Filtering algorithm and Laplacian Sharpening algorithm is designed, and the Verilog language is employed to describe the structure of algorithm. Then, the logic synthesis and hardware test are implemented on Xilinx FPGA. Benefit from the hardware parallelism and pipeline technology of FPGA, the experimental results show that the performance of real-time processing for the video is entirely achieved.