Research On The Mapping Algorithm For Network-on-chip

With the rapid development of semiconductor technology and system integration, more and more IP cores can be integrated on a single chip. To meet the growing performance requirements, Network on Chip(NoC) emerges at the right moment. The emergence of NoC solve a series of bottleneck problems faced by System on Chip(SoC). As a result, NoC has become a hot issue in current academic research fields. The mapping optimization problem of NoC is one of the key problems on NoC design, aiming at mapping the IP cores on the topology of NoC efficiently to achieve the best network performance. The efficiency of the mapping algorithm has a decisive impact on the performance of the mapping result.This thesis first introduces the research background of NoC, and details the key problems of NoC design. The thesis explains the general process of mapping optimization and mapping modeling and summarizes the existing mapping algorithms and the research process of mapping optimization of NoC. Base on the CMesh topology, a single objective mapping optimization model is built with the aim of the minimum energy consumption. It uses Simulated Annealing algorithm to realize the mapping optimization. Given that the cluster topology of CMesh, local overheating could happen in the cluster routers. The problem of the hot-spot seriously affects the system performance. Hence the thesis also builds the multiple objectives mapping optimization model with the aims of low energy consumption and load balancing. Finally, a mapping platform based on Matlab is set up to simulate the NoC mapping optimization. It adopts the CMesh topology and five common applications. The simulation results show that compared with the Greedy mapping and Random mapping algorithms, Simulated Annealing algorithm can reduce significantly the energy consumption and realize the load balancing in the multiple objectives mapping optimization.