Research Of Key Issues On Three Dementional Network On Chip

With the development of network on chip (NoC), more and more components will be integrated into a single chip. Due to several insurmountable problems such as global wire length and packet transfer delay, the two dimensional (2D) interconnection is considered as an inefficient architecture. On the other hand, three dimensional (3D) integrated circuits (ICs) are proposed as a novel approach relying on its potential to improve chip performance, functionality and device packing density. Consequently,3D NoC has emerged as a promising alternative. In this paper, we focus on several key issues in this field, such as simulation platform, communication architecture, routing algorithm and NoC mapping, to optimize the system performance and improve the on-chip communication.The main contributions of this paper are as follows:In early stages of NoC design, analysis of the energy consumption and communication performance is very important since it can make the subsequent process easier. In this paper, we use SystemC to build a system level platform for3D NoC. It is cycle accurate and fast for simulation. Meanwhile, parameters of the system can be changed easily and this provides high flexibility for us. As a result, with its help, we can explore the design space and evaluate the system performance efficiently.A hybrid hierarchical architecture for3D multi-cluster NoC is proposed with the goal of optimizing the whole system performance. Each cluster is made up of hierarchical buses while global connections among clusters are built on the3D mesh topology. The memory subsystem is also divided into several layers and managed hierarchically. Experimental results indicate that the proposed architecture can improve the performance sharply. Especially for a real communication-intensive application, the improvement is more obvious compared to the conventional3D NoC architecture.Based on the architecture proposed above, a statistical time division multiplexing (STDM) based architecture for local system is proposed. And novel packet formats are designed by using the feature of STDM aiming at maximizing the utilization of packets. Meanwhile, the mechanism of waiting is introduced into the network interface (NI) module to improve the performance further. Using the platform built above, experimental results verify that the proposed architecture can save network loads and reduce the transmission delay sharply. In the best condition, the improvement can reach53.3%and79.5%respectively compared with the traditional construction.In3D NoC, how to balance the network load and avoid local hotspot is critical to the system communication performance and reliability. We present an application specific routing algorithm (ASRA) with the help of simulated annealing (SA) algorithm to balance the link load with great flexibility. Experimental results show that, for a real application, the proposed algorithm can achieve an improvement of30.8%in the best condition compared with the order dimension algorithm.A logistic function based adaptive genetic algorithm (LFAGA) is proposed to solve the mapping problem of3D NoC. Considering the increasing size of the target NoC, the LFAGA adopts the strategy of adjusting pc (probability of crossover) and pm (probability of mutation) to improve the convergence speed of genetic algorithm (GA) while maintaining the diversity in the population. Furthermore, the mutation operator picks the ordered genes to mutate instead of random ones in the GA. Compared with another famous GA based mapping algorithm, CGMAP, the LFAGA is always very effective in searching a better solution and leads a faster converge speed in all cases.The energy consumption and link load balance are both taken into account in the multi-objective mapping problem of3D NoC which is different from the conventional one. Since more than one metrics are considered in this case, instead of the traditional single-objective genetic algorithm, a rank-based multi-objective genetic algorithm (RMGA) is adopted in our work to explore the optimal approximation of the Pareto-Front efficiently and accurately. To evaluate the proposed algorithm, the video object plane decoder (VOPD) is used as a case study. The results show that the RMGA can obtain the approximate Pareto-front well and compared with the best results chosen from random generated solutions, the RMGA can achieve an improvement of24.4%and15.4%for energy consumption and load balance respectively.In the final section of this paper, a novel methodology for3D NoC mapping with dummy IPs is proposed. The methodology consists of three phases. In the first phase, we choose part of real IPs and divide them into several smaller dummy IPs. In the second phase, we connect the single real IP to multi routers with the help of dummy IPs. And in the last phase, we explore the routing flexibility among IPs to make the solution better. And in all these phases, simulated annealing (SA) algorithm is used. The experimental results show that, for energy consumption and network load balance, the proposed methodology results in average of22.1%and18.1%improvements respectively compared with the conventional one.