A Study On Wafer Edge Si Peeling Induced 0.18um SOC Low Yield

With the development of integrated circuit manufacturing technology, SOC has been rapid development. Company introduction in the process of 0.18um SOC technology, the biggest problem is the low yield issue at wafer eight o’clock. In order to solve this problem, the thesis carried out the systemic study, find out the low yield reasons and puts forward the technical ways to solve the problem.In this thesis, use a large number of wafer defect scanning with KLA and COMPASS, firstly find wafer eight o’clock defect map at CO-DEP pre-clean stage, the defect map match with wafer low yield map perfectly. After analysis with OM and SEM, find the defect is about 0.2um Si peeling. Through the further observations of wafer edge, find the defect peeled from the eight o’clock position of wafer edge. The results found, mainly caused by 0.18um SOC low yield is the silicon peeling from eight o’clock at wafer edge.After the observation of a large number of wafer edge, find two main problems:the extra pattern and the discolor after backside etch. So form two kinds of fail mode to analysis wafer edge Si peeling:one is edge wash not completely caused by extra pattern, the extra pattern form defect source in the following process; two is the backside wet etch damage wafer edge SiO2, the following SIN dry etch damage the Si due to the absence of SiO2 as the stop layer. Through the optimization of wafer edge PR cleaning process and optimization backside wet etch parameters, found the second failure model is the main causes of Si peeling.For 0.18um SOC mass production issue, this thesis put forward a temporary solution, namely, by increasing the cleaning process to remove silicon particles on wafer surface, after the temporary solution, main peeling has been removed, but not eliminate the defect source.In order to effectively solve the problem of silicon peeling, this thesis put forward to skip the SAB backside wet etch, eliminates the damage of SiO2 at wafer edge, in the SIN dry etch, wafer edge silicon not suffer damage because of the Si02 as a stop layer. This method improves the wafer edge conditions, thoroughly solves the problem of wafer edge Si peeling. After using the new technology, increase the average yield 10%, completely solve the 0.18um SOC low yield issue.