Research Of K-band PLL Frequency Synthesizers

With wireless systems becoming diverse, the demand for low cost frequency synthesizers is growing, and the desire for information and entertainment for anytime and anywhere also increases the demand for higher data rate. With the decreasing size of CMOS technology and the improvement of integration, there are trends that the technology of Group III-V and Si Ge have been replaced by CMOS, which is a good choice of the monolithic integrated circuit. Because of the high division, realizing integer frequency synthesizers, which both meet the requirements of low noise and rapid locking is very challenging in CMOS technology.PLL frequency synthesizer is an important module in transceiver, which exists in most of the wireless communication system, and it is most widely used for up-conversion in the transmitter and under-conversion in the receiver. In this thesis, the main topic is the research and design of a K-band PLL frequency synthesizer.This thesis first briefly introduces the application of PLL frequency synthesizer, and the research situation at home and abroad, then gives its important performance specification, and determines the loop bandwidth and noise transmission characteristics of various modules through the analysis of the loop transient response and the transfer function of noise contribution to the output, then determines the loop filter parameters.A 20G~22GHz PLL frequency synthesizer in TSMC 0.18μm RF CMOS technology is designed. By using coarse tuning capacitor array, fine tuning varactor and phase noise optimization method, the schematic and layout of voltage controlled oscillator(VCO) has been completed, and the simulation results show that the frequency range is 20G~22GHz, the average gain is less than 300 MHz/V and the phase noise is less than-110 d Bc/Hz at 1MHz offset. Based on the conventional charge pump(CP), an improved CP was completed, the tuning range of which is from 0.5V to 1.4V and a good match of charge and discharge current is obtained. A compromise between phase noise and spur is obtained by adjusting reset path delay of the phase frequency detector(PFD). Based on the conventional current mode logical divider(CML), a novel structure by adjusting the current proportion of the sampling branch and latches branch is proposed, then a wider bandwidth is obtained, and the layout of first three cascade CML dividers was completed, realizing the division of 8. With the combination of 4/5 dual-modulus frequency divider and the P, S counter,continuous adjustment from 50 to 55 digital frequency divider chain was completed, realizing the 400 MHz channel width.In the end, the system level simulation results show that the loop locking time is less than 15μs, and the phase noise is less than-105 d Bc/Hz at 1MHz offset from the carrier, meeting the requirements of the project.