Design Of Embedded Ethernet Interface Based On FPGA

The rapid development of computer and communication technology,stimulating each field in progress,especially in the field of aviation.A small amount of information collection,record and display has been unable to meet the demand of airborne data acquisition system,is to a large number of real-time signal recording,processing,storage and transmission direction.A large number of sensors installed in the airborne data acquisition system,these sensors can capture the flying of environmental information,including altitude,air pressure,temperature, wind direction etc.The flight environment through the sensor will be exported to digital level,the information will be changed through the signal sampling,quantizing,coding and other steps,finally the coding element form with the real-time transmitted into the computer for processing,analysis,storage and display through the Ethernet.As the core of data acquisition system,a microprocessor typically offer Ethernet interface,when a large collection of data arrives,the deal with the contradiction between the task and the network transmission is more and more outstanding.In this paper,the real time transmission of a large amount of analog signal need to processor constantly running,considering reduced the processor of computing pressure,the rational use of resources of FPGA acquisition system and the strict requirements of flight environment put forward for airborne equipment volume,power consumption etc.Based on Embedded Ethernet as the foundation,proposed the embedded Ethernet interface design plan based on FPGA.The main work is as follows:1,In this paper, we completed the design based on the characteristics of FPGA’s high performance,wide application,flexible programming,using the method of hardware and software collaborative program.Taking Altera company Cyclone III series as the platform, Built in Nios II soft core processor as the core contains a variety of peripherals which called System on a programmable chip(So PC),one of the most major peripheral is the core of media access controller for Ethernet(MAC).In use of Triple Speed Ethernet IP nucleus provided by Altera can realize of Ethernet MAC protocol in FPGA,and provides a standard medium independent interface(MII).The MII interface linked together with external expansion of the physical(PHY) chip,finally complete the network interface design.PHY chip is DP83640, which has the advantages of small volume,low power consumption but powerful,and provides reduced media independent interface(RMII).2,The bottom of the network communication is the design of network interface.In order to achieve the complete Ethernet communication,in software design,having completed the driver design of triple speed Ethernet MAC and DP83640,and transplanted the light weight TCP/IP protocol — — Lwip.In order to reduce the use of memory,this paper transplanted the Lwip protocol without operating system.According to the protocol stack,having achieved the data transmission of UDP,and provides the upper application program interface.The design of Embedded Ethernet interface in FPGA based on the demand of airbone data acquisition environment,making full use of the FPGA’s characters of high-speed,real-time and programmable.through testing,the network transmission performance has reached the requirements of system parameters.