Flip-chip Physical Design Application Technology Research

Nowadays more and more electronic products are moving in small, portable, network -oriented direction, but the main trends in electronic product design has become faster, lower power consumption, lighter weight, smaller. With such as CPU, SOC products such as the rapid development of high-end circuit, the chip more integrated, more complex functions, I/O numbers increased dramatically increase the operating frequency of the signal time delay will be more demanding requirements Therefore, chip packaging technology are raising increasingly high requirements. Flip-chip has become the high-end devices and areas of high-density packaging often used packages. This package directly to the active area of the chip substrate, a wafer is mounted upside down directly to the printed circuit board from the wafer input and output interfaces leads to four weeks, the length of the interconnection is shortened, reducing the capacitance resistance caused by the RC delay, effectively improving the electrical properties. In all surface mount technology, the flip chip can achieve the smallest and thinnest package.With deep into the design process more advanced 40-nanometer and 28-nanometer process, the 10 number whin chip unit area are increasing as well as increasing of low-power requirements. On the other hand, the design of functional requirements more diverse, such as CSP, POP and other diversity package, making the flip- chip design more complex. The traditional flip- chip design is mainly based graphical interface and manual full-custom, in practice, when faced with high complexity of the project, the workload will be very large; when the project’s design cycle is very short, the timing of the work on will be very nervous.This paper attempts to apply the Cadence EDI (Encounter Digital Implementation) TCL-based language created from data preparation to bump array generated, the connection relationship establishing, and then RDL routing, and finally to check LVS/DRC. This method could help the designer evaluate bumps resources effectively at early stage, while also reducing the working hours of the entire design. This paper also analyze and compare different types of power/ground bump array, in addition, will also summarize design experience for collaborative design of the diverse functional requirements.Currently, automated design methodology and associated TCL script, has been applied in Marvell’s four 40nm mobile chip design (mobile design) and two 28nm mobile chip design and successfully taped out. In the actual project work, it will help designers improve the work efficiency, shorten the design time required...