| In recent years, Liquid Crystal Display (LCD) industry has been developing rapidly, andthe manufacturing of LCDs with larger dimension, lighter weight, lower power consumption, andhigher resolution becomes the industry technology development trend. LCD modules are common-ly assembled using the Chip-on-Glass (COG) technology, the interconnection of which is realizedby Anisotropic Conductive Film (ACF). The assembly has the features of package high-density, inwhich the IC bump pitch reached25μm, and process parameter complicacy. During the processdesign and optimization of ACF-COG interconnection, the interconnection resistance has been thekey indicator of product interconnection performance because it has instability feature and is easyto degrade, and it will lead to serious reliability problems if having no effective inspection andcontrol methods for the resistance. The interconnection resistance is decided by many factors,including the bonding process, equipment characteristics, packaging material properties, driverIC/pad design, and etc. How to achieve lower, uniform and controllable interconnection resistancewithout bump short-circuits has been one of research hotspots in COG packaging. Currently, theinterconnection is mainly evaluated by making dummy chips and then measuring their resistanceafter bonding and during reliability test, in which it depends on the operator’s experiences and istime-consuming/manpower-consuming. The evaluation is lack of effective quantitative analyzingmethod. Therefore, there is an urgent need for COG packaging to develop an automatic estimatingand quantitative analyzing method of interconnection resistance, especially for the future fine-pitchCOG bumps.This thesis carries out studies on the technique of automatic interconnection resistance esti-mation for ACF-COG assembly on the basis of analyzing the current COG packaging process andinterconnection resistance modeling. It mainly focuses on the interconnection resistance model-ing using particle conductive area and the automatic acquiring method of bump conductive area,and finally offers the support on automatic resistance motoring and process optimization judge-making for the higher density LCD module assembly. Considering the urgency of the domestichigh-density COG flip chip machine development, the thesis made studies on the flip chip ma- chine design on the basis of COG packaging process characteristics, and carried out the test andvalidation of interconnection resistance estimating method on the developed machine. The maincontents and achievements are as follows:Firstly, the idea of interconnection resistance estimation based on conductive areas was pro-posed, and then the conductive particle resistance model of ACF-COG assembly based on conduc-tive area was subsequently proposed, in which the resistance includes the constriction resistancebetween the particle and bump or pad, the bulk resistance of particle metal shell, and the tunnelingresistance of contact plane. With the model testing and resistance value comparison, it shows thatthe estimation value of interconnection resistance using the model fits the actual measured onebetter than using the other published models. Based on the single particle resistance model, theresistance model of IC bump and substrate pad interconnection with multi conductive particles wasproposed, and it counted in the extra resistance caused by the electric field potential distortion be-cause of particles’interaction and edge effects. Through this, a more precise computation modelwas achieved, and can be used to calculate the resistance once the conductive areas and positionsof the particles under the bump were acquired.Secondly, the COG bump interconnection resistance estimation method based on machinevision was proposed, which is designed to acquire bump conductive area automatically. Consider-ing the characteristics of more line probability at the bump edges, the automatic bump boundaryand region extraction method was proposed, which combined the edge detecting, energy gradientand bump geometric features, and can eliminate the interference of edge detecting from the par-ticle agglomeration and bubbles. After acquiring the bump region, the particle conductive areasof bumps can be recognized and computed using image morphological operation, and then canbe used to estimate the interconnection resistance accurately with the resistance model. The testusing bump pictures and result analysis reveals that the bump region extraction rate surpasses95%with the proposed method. In the respect of conductive particle counting, its accuracy rate reachesaround94%comparing to the manual check values, and it has obvious advantages over manualcheck especially in the case of particle distinguishing difficulty due to excessive pressure or someimage noise existence. As for the interconnection resistance estimation, it achieved an accurateestimation for bumps using the particle conductive area and position.Thirdly, according to the ACF-COG packaging process characteristics of high-density, com-plex process, and high alignment accuracy, a new structure for high-density and high precisionflip chip bonder is proposed. The machine is designed with IC upload round conveyor, panel u-pload component, high precision alignment pre-bonder, and the main bonder with dual heatingpressure head. The heat pressure head structure is designed and optimized to achieve a uniformtemperature distribution and a good flatness on the bonding head plane. Through the simulation ofheating transfer and thermal strain and the structural parameter re-designing, the theoretical surface temperature difference and plane flatness of bonding head were controlled at3.39C and2μmrespectively, and meet the equipment bonding requirements. According to the machine schematicdesign, the vision systems of IC pick-up and pre-bond alignment were designed, and then the ICupload mechanism, bonding assembly and motion stage were designed, and finally the machinemechanical structure design was completed.Finally, according to the functional and structural design of flip chip bonder, the control sys-tem was designed. With the analysis and optimization of control sequence, the process plan ofdouble panel production in12seconds,11.75seconds in actual testing, is achieved. The precisiontest of stage positioning, visual alignment, and the heating pressure stability of bonding heads werecarried out, and all the results show the positioning and heat-pressure accuracy achieves the designgoal. The machine was used to bonding the dummy IC to LCD glass substrate; and228bump pic-tures acquired from the testing modules were used to test the interconnection resistance estimationmethod. The experimental results show that the method has advantages on estimating accuracy andbump performance analysis, and can output the data and make statistics on the bump conductivearea, each particle conductive area and bump particle number. The bump interconnection resis-tance and bonding force estimated by the technique are very near to actual measured values. In themeantime, the method can extract the defect bumps promptly, and provides the convenient way forCOG package process analysis and optimization. |
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