Research Of Efficient Page Replacement Algorithm Based On Hybrid Main Memory Architecture

In the design of modern computer systems, energy consumption has become more and more important factors. And the stored energy is one of the most important part that can’t be ignored. As the mainstream of main memory, Dynamic random access memory (DRAM) is nonvolatile memory. DRAM has very high static power consumption caused by the refresh, which has seriously restricted the development of storage system.Phase change memory (PCM) has emerged as one of the most promising technologies to incorporate into the modern memory hierarchy of computer systems. The static power consumption PCM of is only about 1/1000 of DRAM. And its storage density is about 4 times of DRAM. PCM is byte-addressable memory similar to DRAM which determines the PCM has potential that can be used as main storage. Unfortunately, PCM has two critical weaknesses that prevent it from substituting DRAM memory totally. First, write access time and energy consuming of PCM is greatly higher than the read operation due to its physical characteristics. Second, the number of write operations allowed for each PCM cell is limited and current write endurance of a storage unit is only about 106-108, which leads to limited lifetime of PCM. Therefore, considering the fast read and write speed of DRAM and the high density and low static power consumption of PCM, the existing researches mainly focus on how to design a hybrid memory architecture composed of DRAM and PCM, which is more reasonable and efficient.Existing solutions can be mainly divided into two solutions. One way is to use smaller capacity DRAM as the buffer and PCM as main memory. This will not only exploit the advantages of PCM that has low static power consumption but also obscure the deficiencies that it has high write operation delay and power consumption. But in this framework, once some procedure that has low locally access, frequent cache replacement will bring huge overhead. This will greatly affect the efficiency of the system. The second idea presents both DRAM and PCM at the same main memory level, constituting a unified memory address space. The operating system perform address translation by the same page table. Because this scheme does not have extra hardware, it has smaller effect on existing system. At the same time, compared to the first approach, it can provide higher storage space. So many existing researches are committed to this kind of architecture. As main memory system is the intermediate between cache and physical memory, a reasonable choice of the page replacement algorithm is necessary for hybrid memory. However, in hybrid memory architecture, we also need to replace write-bound page to DRAM and replace read-bound page to PCM to ensure the performance of the system. So the traditional page replacement algorithms are not directly applicable. The design of page replacement algorithm becomes one of the key researches of hybrid memory system.This paper first analyzes the prediction mechanism of write operation. We find that in most cases, forecast by write frequency display better effect than temporal locality. So when we use the temporal locality together with write frequency and propose an efficient page replacement algorithm. For pages in PCM we take passive policy to replace the appropriate page into DRAM. When DRAM has no free page, we call the improved CLOCK algorithm to take page whose write frequency is low into PCM. On the other hand, we also propose a wear-leveling algorithm to ensure the write counts on PCM more even.To evaluate the performance of proposed algorithms, we exploit the GEM5 simulator, a highly configurable architecture simulator. We modify the GEM5 simulator source code, making it to meet the need of the hybrid memory architecture. Experimental results show that the proposed algorithm can effectively reduce the number of write on PCM, shorten the execution time and extend the life of PCM.