Research And Design Of A Zoom ADC

As the bottom stage of Internet of Things, sensor is now playing an increasingly important role in the development of Internet of Things. Sensor has the function of transforming natural non-electrical signal into electrical one in the form of analog signal with an amplitude of merely several mV. Hence, an amplifier is needed to read out the small signal and converts it into digital signal for further processing. According to the application requirements of temperature sensor, a Zoom ADC is proposed in this paper. Since the signal produced by sensor is almost close to DC level with a frequency of only several Hz, offset noise,1/f noise and drift noise can easily blend into signal band, which leads to the degrading of resolution. Therefore, the proposed Zoom ADC should be able to not only filter out the in-band noise, but also have the advantages of high resolution and high linearity.The proposed Zoom ADC is mainly composed of SAR ADC and Sigma-Delta ADC, whose operation is divided into two steps:coarce conversion and fine conversion. SAR ADC is firstly used in the coarce conversion to narrow down the signal margin. Then Sigma-Delta ADC is applied in the fine conversion to further convert the signal into higher resolution. Finally, the resolution of Zoom ADC is achieved by the combination of coarce conversion and fine conversion. This paper combines the SAR ADC and Sigma-Delta ADC into a single circuit, performing different functions in different cycles, which simplifies the circuit structure, reduces the power dissipation and improves the integration density. In SAR ADC, base on the bottom plate sampling technique, a charge-redistribution DAC is proposed. The design processes of sample and hold circuit, DAC, comparator, SAR logic and digital control logic are introduced. With the use of bottom plate sampling technique, clock feed-through and charge injection caused by non-ideal factors of MOS switches are largely reduced, which leads to the improvement of resolution. As the fine conversion by Sigma-Delta ADC is performed after the coarce conversion, the circuit complexity of Sigma-Delta ADC is highly degraded. Thus, a single loop one stage one bit structure is implemented in the Sigma-Delta modulator. With the use of switch capacitor fully differential integrator, the even order distortion and noises from substrate and power are largely reduced, which results in the improvement of accuracy. Finally, the layout of Zoom ADC is proposed, as well as the definitions of the chip pin. In addition, the decimation filter in Zoom ADC has a big impact on the power dissipation and area comsuption of the chip. The on-chip design of it will largely increase the power consumption and chip area. For flexibility, the decimation filter is implemented off-chip.The whole circuit is based on the Global foundries 0.18μm CMOS technology with a supply voltage of 1.8V and sampling frequency is 2.5 kHz. Simulation results show that SAR ADC has the resolution of 5 bit, while the SNR of Sigma-Delta ADC can reach 45.1dB and the ENOB is about 7.2 bit. Therefore, Zoom ADC has the resolution of 12 bit while its power dissipation is merely 0.5mW.