Research And Implementation Of XML Parsing Technique

After more than ten years of development, XML has become the most popular Web data storage and exchange standards. XML got a rapid growth on the proportion of network traffic, at the same time brought a big load pressure to the enterprise network, processor and storage structure. Traditional XML software-based approach has become increasingly difficult to meet the demand for network development. As more Web service application has used network to exchange XML messages, XML communication processing will inevitably develop from application server software level to hardware level. The technology in close related to the issue is the XML processing transplantation on chip.Parsing is an important part of XML processing. XML parsing is a method that extracting the element、attribute and content in XML document, and then using the information for further operations, including an examination of whether the object document is well-formed, or whether the element or attribute is valid and so on. For those who need to deal with large amount of data applications, this technology is particularly important. Choosing a proper parsing technology has a great influence on the performance of application system. Incorrect parsing would lead to excessive memory consumption and long processing time, which greatly affect the system’s overall performance.This paper presents an efficient hardware implementation method to solve the problem of performance bottleneck when implemented in software. By analyzing the XML parsing procedure, we can find that in the three phases of XML parsing, the first two phases, Well-formedness checking and Schema validation, are the most resources-consuming, because they contain repeated document traverse operations and a large amount of validity and grammar normative check. Therefore, this paper does not seek to achieve a complete parser, but rather to focus on the validation phase of realizing XML parsing processing, completing hardware module design and implementation in the phases of well-formedness and Schema validity check. All the hardware modules are developed by Verilog hardware description language. Simulation and testing results show that the design meets the requirements.