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Research On Heteroepitaxy Based On Nano-Patterned Substrate

Posted on:2015-09-24Degree:MasterType:Thesis
Country:ChinaCandidate:Y B LiFull Text:PDF
GTID:2298330467963779Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
Heteroepitaxy of high quality epilayers on the specific substrate material can take advantages of the respective strengths of the two material systems to achieve high-performance optoelectronic integrated devices and chips. However, high dislocation density is present in the epilayers due to large lattice mismatch and other problems, which will seriously affect the performance of the optoelectronic integrated devices. In recent years, fabrication and application of the nano-patterned substrate have attracted widespread attention with the development of nano-technology. Studies have shown that heteroepitaxy on nano-patterned substrate (referred to as "nano-heteroepitaxy") can effectively reduce the dislocation density and improve the crystal quality of the heteroepitaxial layers.Therefore, this article carried out metalorganic chemical vapor deposition (MOCVD) growth of large mismatched system GaAs/Si, InP/GaAs using nano-heteroepitaxy method. The main work and achivements are listed as follows:(1)Periodic array of round-pillars with diameter about370nm were fabricated on Si substrate by soft UV nanoimprint lithography and reactive ion etching (RIE). And then1.8μm-thick GaAs epilayer was prepared on this nano-patterned Si substrate and planar Si substrate using three-step growth. Measurement indicated that the etching pit density (EPD) of GaAs epilayer was able to decrease from about109cm-2to107cm-2implementing this nanopatterned Si substrate. Transmission electron microscopic (TEM) observation revealed that most of the threading dislocations of GaAs epilayer were trapped near the top of the round-pillars. This attributed to three reasons:dislocations can be trapped by the sidewall of the round-pillars; dislocations can bend horizontal on the patterned substrate; epitaxial areas was decreased to nanoscale range. Forthermore, the dislocations in the GaAs epilayers were further reduced by introducing thermal cycle annealing.(2) Periodic array of round-holes with diameter about328nm were fabricated on the SiO2masked Si substrate by soft UV nanoimprint lithography and RIE. Suitable cleaning process conditions of SiO2/GaAs nanopatterned substrate was obtained, which can clean the substrate without damaging the SiO2mask. Heteroepitaxy of GaAs was carried on this nano-patterned Si substrate and preliminary experimental results were obtained.(3) SiO2nano-gratings w’ere fabricated on GaAs(100) substrate by electron beam lithography and reactive iron deep etching using Cr as the protective layer. Wet etching was also used to improve the morphology of the SiO2sidewall after RIE process. The final result showed that SiO2/GaAs nanopatterned substrate with aspect ratio more than1was achieved. Heteroepitaxy of InP was carried on this patterned GaAS substrate and preliminary experimental results were obtained.
Keywords/Search Tags:nano-patterned substrate, nano-heteroepitaxy, GaAs/Si, InP/GaAs, MOCVD, EPD, TEM
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