Research On Optimization Of The STT-RAM Cache

Cache acts as an available function unit which can release speed difference between processor and memory in computer architecture. With the rapid development of semiconductor manufacturing processes, the traditional techniques which use SRAM as Cache is restricted by the memory cell area, the static power consumption and other factors. STT-RAM-a novel nonvolatile storage material, it has low power consumption, fast read speed, high-density, multi-level cell capacity and other characteristics. In today’s era of high-performance computing, the fast computing speed of processor is unquestionable, so the performance of memory has become a major bottleneck affecting overall system performance. The STT-RAM has been seen as the most promising alternative for cache to replace SRAM memory material since appeared. However, due to STT-RAM’s write speed is relatively slow and write energy consumption is relatively high, so the scope of STT-RAM research is mainly focuses on reducing STT-RAM Cache write latency, improving system response performance and reducing STT-RAM’s write energy.Based on the characteristics of STT-RAM, we first analysis the relationship between several important parameters of STT-RAM, and then gives which kind of parameters of STT-RAM is suitable for L1Cache. Through the experiment, in the set of STT-RAM data retention time, we do segmented statistics of the data block in L1Cache. We found that refreshing most data stored in the data block is in vain. In this paper, we proposed a counter-based strategy to avoid refresh, and then do feasibility analysis of the NRS strategy and detailed design of the entire monitoring process of the counter, processing methods and data processing method. Experimental results show that the NRS strategy can achieve the goals of reducing write energy and write counts, at the same time, obtain system performance by1.5%.Focuses on the character of different data retention time and different write energy consumption of STT-RAM, we adopt the mixture design of different characteristics STT-RAM as L2Cache, which divided into two different parts based on write latency. And then dynamically monitor and management the data stored in each section. According to STT-RAM L2Cache architecture proposed, we put forward the corresponding data migration management strategy, which is committed to make data blocks within different reading and writing characteristics separated stored, thereby reducing the writes count of L2Cache and reduce the write energy consumption. Experimental result shows, compared to design that adopt SRAM L2cache, hybrid architecture of STT-RAM L2Cache design in this paper has performance fallen by2%, but better than pure STT-RAM design, performance gain is about6%. Compared to the other baseline design, our design can significantly reduce write energy.In summary, we optimize the write operation and write energy on STT-RAM Cache by NRS method and OFMS method in this paper. The experimental results show that the optimization strategy can reduce the energy consumption of the STT-RAM Cache effectively.