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Design And Implementation Of Bus Lane Detection System Based On FPGA

Posted on:2012-04-09Degree:MasterType:Thesis
Country:ChinaCandidate:X DongFull Text:PDF
GTID:2298330467478613Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Video vehicle detection technology in today’s transportation is a hot spot of research and application. It combines image processing, computer technology, artificial intelligence, advanced technology and other subjects, and have obvious advantages in information processing, and the future development is potential. With the traditional vehicle detection methods, video-based vehicle detection technology has unparalleled advantages. Computer vision for the transport system provides a more intuitive and convenient means of analysis, and a lot of traffic environment information from the visual, and dealing with computer vision technology is a natural choice. The use of FPGA can take full advantage of parallelism of hardware and improve the speed of image processing in essence so that image processing with the large amount of data can achieve real-time ability. SOPC technology can make the design flexible, trimmed, scalable and upgradeable.This paper designs a bus lane detection system based on FPGA. The system uses DE2development board of Altera as the hardware platform. CMOS image sensor monitors the environment in real time. VGA displays the monitoring environment. When community vehicles come into the monitoring road, then the red rectangle on the monitor will label the illegal invasion of vehicles in order to notify monitoring staff for processing.Using a synergistic manner through software and hardware, the entire system is realized. Hardware:first of all, on the basis of the requirement analysis, the paper designs and implements all the modules, including image capture module, SDRAM module, image display module and vechicle detection module, and then the paper builds the system in verilog hardware design language by Quartus Ⅱ., using the SOPC builder in Quartus Ⅱ to construct the vechicle detection module. Finally, the thesis builds the entire hardware system by Quartus Ⅱ. Algorithm:the paper adopts Hough transform algorithm to identify lane to determine the identification area, and then uses frame difference algorithm and erosion and expansion algorithm for vehicle detection, and uses line coding segmentation algorithm for region segmentation, and finally extract the partition characteristics of the vehicle to match with the template to output. Software:the algorithms are programmed and debugged by C code in the Nios II IDE environment. After a period of debugging and running, the system realizes the better results.
Keywords/Search Tags:SOPC, Nios Ⅱ, FPGA, lane detection, vehicle detection
PDF Full Text Request
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