Improvement Of Design Verfication Flow For Complex IC

Integration of the X86system on one chip is the technical trend. Thenumbers of IP grow to more than100and the verification environmentbecomes more and more complex. As a result, the efficiency of team workbecomes low; for example, the slow speed of MAKE caused by thousandsof MAKE nodes, the complexity of file list management for numerous filesin the environment, the slow simulation speed for the large RTL designscale, and the instability of the database caused by access from more than100people in the same time.Firstly, the thesis studies the major operations of the front-end designenvironment, gives detail part impacting the productivity, and thenanalyzes the effect of each kind of operation error and possibility of usingparallel tasks scheduling to resolve the problem.Secondly, the thesis analyzes the reason for the low efficiency of thenormal MAKE system and presents an optimal process to fix the issue.Some important steps like the task description, task partition, selection ofparallelism degree, load balancing and the detection of infinite dependencyloop are discussed in detail, the optimized MAKE system is implementedbased on these steps. The experiment verifications show that the optimizedMAKE system speed is improved.The unstability and the inefficiency of big database with multi-IP arecritical, a new mechanism to resolve this issue is presented. By thismechanism, the quality of the database will be automatically checked aftereach user modification, and an audition program on database server is usedto ensure this quality checking should be succss.Finally, after discussing the impact of IP-XACT specification, the thesis designs a feasible and format language, and implements the parser,the application program of this new language to support VCS compilationand VIEW configuration. The simulation shows us that the speed isaccelerated10times faster than before.