Research On AES Algorithm And The Realization On FPGA

The application-oriented services based on computer network have been rapidlydeveloped in the period of vigorous development of computer network technology.The internet information security has raised a common concern in the field of researchand commerce. Despite the current methods and types of encryption are complicatedand their own system of norms have developed in various industries, the securityproblem is still an important issue in the information age. As the speed of networkdevelopment is faster than data security thoughts, the security issues became moreprominent today as the network is widely applied. Since a lot of sensitive informationis exchanged through computer networks and the network is quite open, it makesusers in urgently need to transmit information safely and efficiently. AES algorithmcan solve the existing problem in data privacy protection and Authentication. So thefurther studies on security issues of AES algorithm have great significance.This paper studied the theoretical layer and implementation layer of AESalgorithm. First, this paper introduced the basic principles of the AES algorithm andexisting effective attack methods. Then it proposed improved methods to S-box of theAES algorithm to solve the problem that affine transformation cycle is too short,iterative output cycle cannot fill the space,and the item numbers of mathematicalexpressions are few appearing in AES algorithm. Finally, this paper presented AESencryption and decryption system designing program based on FPGA and tested asimulation of the encryption and decryption functions of the system using ISimSoftware which comes with ISE development tools.The improved S-box method enhances the resistance to attack based on theexhaustive method by using91groups of affine transformation pair building basiclibrary. In addition, this method uses the second-order affine transformation toincrease affine transformation cycle to16, the Iterative output cycle to255, and theitem numbers of mathematical expressions of forward S-box affine transformation to255, so that the resistance to attack based on the mathematical characteristics isenhanced. The FPGA designing uses ISE of Xilinx company as Development Kit andXilinx’s Spartan3A DSP series as hardware development board. It also uses anon-pipelined architecture of iteration structure as of the encryption system based onAES algorithm, and the feedback mode as the working mode. The design of AESencryption and decryption system included five core modules: SubBytes, ShiftRows,Mixcolumns, AddRoundKey and KeyExpansion, as well as the overall controlmodule. The simulation data shows this design can complete the function ofencryption and decryption based on AES algorithm, and confirms the correctness of the algorithm, and achieves the improvement purpose of the algorithm.