Research On Data Driven Multi-core Processor Based On Crosspoint-queued Routing

It has been the trend of multi-core procssors research directions on how to coordinateamong multi-core systems effectively and how to implement inter-processor communicationaccurately. The challenge in multicore era is not the design of processor itself, but theinterconnection among each of those cores, parallel programming and cache coherency. As thenumber of processor cores become larger, power consumption and delay of interconnection areparticularly pronounced. The traditional serial programming model has been not suitable for usein multicore parallel programming, multicore parallel programming is going to be a challenge.Cache coherence is particularly important in multi-core processors system. Each processor coremay have a copy of the same data. Once the data of a copy is modified, others should be updatedto maintain data consistency to avoid errors.For the issues above, a multi-core processor prototype which supports data drivenmechanism and functional language programming style is presented in this essay. The multi-coreprocessor consists of sending match module, general processor cores, data driven module andcrosspoint queued on-chip router. Data driven module is responsible for data matching and dataintegrity detecting. Router on chip realizes communication among processor cores or clusters.The experiment results show that multi-core processor prototype supports the functionallanguage programming style of C language. The executing of every C code segment is theoperation of pure function, which eliminates the sharing variables among functions and partlyreduces the complexity of parallel programming. Meanwhile, the data driven mechanism has nostrict restricions over executing order, which fully has excavated the potential parallelism ofalgorithms. According to the test, the multi-core processors based on data driven mechanism canobtain linear accelerate ratio with the increase of computation source.The proposed design in this essay has effectively combined the fine-grained of data flowcomputer and sequence control order of control flow computer, which is a solution withperformance, flexible design and use, low cost and power consumption. The adopted data streamfunction language is easy for parallel software development, which effectively solve the problem of software development lagging behind the hardware development. The essay uses the QuartusII and Modelsim to build RTL hardware circuit, then implants corresponding multicore system inAltera’s DE2-115FPGA development board, finally completes the simulation, synthesis,verification test of interconnection architecture.