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FPGA Implementation Of Video De-noising System Based On Wavelet Transform

Posted on:2015-06-21Degree:MasterType:Thesis
Country:ChinaCandidate:W Z WuFull Text:PDF
GTID:2298330422981919Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
When video surveillance system using, the interference of various factors causing noise,affecting The quality of the image and the subsequent processing. Thus, real-time removingimage noise is a research project of video surveillance system to further improve the videoimage quality.Based on the FPGA hardware platform, designed a real-time noise reduction systembased on wavelet transform. The main work of this paper is as follows:1. Through the system’s real-time and DDR2bandwidth analysis, combined with thecharacteristics of the algorithm, dividing the system function and using three pipelinedparallel architecture, proposing the system’s overall FPGA implementation framework.2. When designing hardware structure of critical module, studys5/3wavelet transformof lifting algorithm, there being the critical path length and low resource utilization problemin direct structure, using the parallelism between the forecast and updatethe and the methodof hardware reuse, proposing one-dimensional wavelet transform folded pipeline structure,optimizing the data path and decreasing hardware resources. On the hardwareimplementation of the inverse wavelet transform, guaranting real-time requirement,a threeparallel cross wavelet reconstruction architecture is proposed, controlled by a state machine,so that completed within a time frame, reaching performance requirements. On thehardware implementation of Bayes thresholding algorithm, to decompose the algorithm step,using the method of parallel processing, a fast calculation model is established.3. When DDR2using, through the corresponding cache control scheme, the entirecontrol is divided into four parts, including cache interface part of writing or reading DDR2,the bus arbitration module, DDR2controller, through four parts cooperative controling,achieving a high-speed memory access requirements of multi-channel data.Based on the above designing work, writing Verilog HDL hardware circuit description,and the contrast texts the correctness of the design between Modesim and MATLAB verify,the highest frequency reaching178.76MHz after systems integration. On a hardwareplatform based on Stratix III FPGA, verifys the feasibility of the system to1920*1080at60frames/s video de_noise real-time processing.
Keywords/Search Tags:surveillance video, real_time, thresholding de-noising, DWT, FPGA
PDF Full Text Request
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