| Video surveillance terminal is one of the most important devices in the multimedia field. With the rapid development of image processing and microprocessor technology, video surveillance terminal is becoming a smaller, more integrative device that applied in various circumstances and assembled into a flexible network. Despite of the classic solutions of video system based on DSP processor has great performance, many devices have a short life and a high cost in update because of fast upgrade in microprocessor. At present, a new DSP design flow and soft core based on FPGA can remedy the defects and adapt to the trend of video surveillance.According to the idea, a video surveillance terminal system based on FPGA platform is designed and implemented in this dissertation. The main functions achieved in the system include video compression and coding, audio compression and coding, alarm controller, serial monitoring unit and Ethernet transmission. All the works in the dissertation are summarized as follows.(1) Video processing block is the most important part, which consists of video capture, pre-processing, display and compression and coding. The compression and coding block refers to H.264 and utilizes a united development method that consists of MATLAB, DSP Builder and Quartus II. Video intra prediction, integer transform and quantization blocks have been worked out in a FPGA chip. The plans to design each block are proposed firstly, followed by briefly introduction of corresponding technologies of image and video processing. Then the detailed design and implement workflows are described.(2) Based on Nios II soft core processor system, an application program is developed. It implements data allocation, system management and the 10/100M adaptive Ethernet transmission through programming and transplanting LwIP protocol stack toμC/OS-II. The section is composed of the introduction of Nios II's characters, the basic hardware platform built up in SOPC Builder and the process of developing Ethernet transmission program.(3) An audio coding block based on ADPCM algorithm, a serial communication block for RS232/RS485 and 16-channels alarm controller are designed and implemented in the dissertation. By integrating the blocks with small computation into Nios II processor system and executing the audio and video processing blocks independently and parallelly, the efficiency of system is greatly improved.(4) After integrating the software with the hardware, abundant schemes are presented in this dissertation to test the working state of each functional block. The experimental results are analyzed and the conclusions indicate that the system works properly in 100MHz. Compared with a Davinci processor, the system possesses an advantage of lower cost and higher flexibility to basically meet the requirement of future digital video surveillance terminal. |
