Research On Online Self-evolving Approaches Of The Digital System

Combining evolutionary algorithms (EA) with programmable logic devices, Evolvable hardware(EHW) can reconfigure its own internal structure dynamically and autonomously according tochanges of environment to adapt to the new environment, bringing a breakthrough for evolutionarydesign of circuits. However, EHW is not scalable to larger problems and the system reliability is still achallenge so far. In this dissertation, a self-evolving system based on Virtex-5FX board is built, andthe online evolution of combinational logic circuit is performed, and the mechanisms of theevolutionary design of large combinational logic circuits and the selective triple modular redundancysystems are explored.The main research works in this dissertation are as follow:(1) The related works and progresses of EHW are reviewed, and the problems in EHW areanalysed. The virtex-5ML507experimental platform and the development environment to build theself-evolving system are introduced, which include the basic structure of FPGA and embeddeddevelopment tool.(2) The whole design scheme of the self-evolving system based on Virtex-5FX board is given.The virtual reconfigurable circuit and the evolution module are designed, and the evolvable IP core isadded to the whole hardware system. Then the software of the self-evolving system is designed.Finally, the two-bit multiplier circuit is taken as an example to verify the self-evolving system.(3) A parallel evolution mechanism by partition in stages based on inputs and outputsdecomposition is presented for combinational logic circuit. The principle of the evolution mechanismand the design of hardware and software are given. At the same time, two-bit multiplier, three-bit nocarry adder and Con1circuit are taken as the examples to verify the self-evolving system. Theexperimental results show that compared to the classical evolutionary method, it is capable ofreducing the evolution time and evolving combinational logic circuit up to21inputs.(4) To obtain the tradeoff between reliability and resource consumption, the evolutionary designof selective triple modular redundancy (STMR) is researched. The whole design scheme of the STMRsystem is given. And the fault-tolerant strategy is tested on four circuits from MCNC benchmark suiteby designing a SEU fault insertion simulator to introduce errors representing SEUs. The experimentalresults show that it can generate innovative trade-off solutions to compromise between hardwareresource consumption and the system reliability. The maximum savings in area overhead of theSTMR circuit over the TMR design is63%with the same SEU immunity.