The Research Of Parallelism On Multi-core DSP&ARM System-on-Chip

In most recent years, DSPhas been more and more widely used in high performance cloud computing, video surveillance, photoelectric detection, automation and other fields, in consideration of its powerful processing capability, relatively low power consumption and high flexibility. In the development of the past decades, DSP has seen the transforming from the original simple structure, to a structure of multi-core and fusion with microprocessor(s).With the progress of DSP technology, the photoelectric theodolite image processing hardware platform begins to transform from a loosely coupled architecture which composed of multiple single core DSPs and other peripheral circuit, to a tightly coupled architecture which composed of a single multi-core DSP and other peripheral circuit.The 66AK2H12 multi-core DSP+ARM System-on-Chip(SoC) released by Texas Instruments Corporation in 2013 gives a solution to this requirement.While the new solution brings improvement of performance, it also brings problem of parallel programming and resource manipulation. This research work is exactly derived from the demand for upgrading of photoelectric theodolite image processing platform, and mainly focus on how to fully use the system resource in the 66AK2H12 SoC to program, as well as how to exploit the parallelism of the system to improve the program performance. This paper gives an introduction to the research work in the following four parts.The first part is the analyzing of the system architecture, including the processor architecture, memory architecture and inter-processor communication mechanism. The research work showed that with high speed on-chip memory, intranet and data transfer engines, the SoC is powerful in data processing.Besides, thethorough interrupt control system and inter-processor communication mechanism makes it possible for multi-core parallel processing. Based on the analyzing, this part ended with some code optimization strategies concerning parallelism and memory architecture on the SoC.The second part is the researching of memory parallel accessing performance. It firstly summarized the bandwidths of important system nodes, and then carried out some tests and analyzing for the performance of parallel accessing on multicore share memory and DDR3 memory, which initialized by the crucial system masters, i.e., ARM, DSP and EDMA. The tests showed that the on-chip memory is sufficient in bandwidth for parallel accessing by multiple system masters and that using cache technology or auxiliary memory accessing peripherals such as EDMA could greatly improve the memory performance.The third part is the studying of parallel programming method, including the design scheme and programming model.An example of image edge detection algorithm introduced in this part demonstrated how to use the design scheme and programming model to a specific application. The example also showed that OpenMP programming model works well on applications use both DSP and ARM processors, and that good acceleration performance could be achieved while multiple coresparticipating in processing.The last part is the introduction of the starting up procedure of Linux operating system(OS) on the 66AK2H12 SOC and the steps to migrate the OS to the SOC.