Power Factor Correction Technology Research For Wireless Power Transfer System

This paper is focused on power factor correction technology of transmitter and receiver in wireless power transfer system(MCR-WPT). Improvement of the power factor at transmitter may enhance the power utility of the power grid for the purpose of power-saving. The high frequency noise, produced by the MCR-WPT system, also can be kept from the power grid. Improvement of the power factor at receiver may enhance the power utility, and reduce the cost of the high frequency power amplifier directly.At the receiver of MCR-WPT system, a novel pick-up with improved power utilization is designed. An additional inductance is applied to the conventional pick-up to improve the power utility. A equivalent circuit of the traditional pick-up is developed based on the characteristics of MCR-WPT system and its drawbacks are analyzed. Then an equation of critical inductance of the novel pick-up is derived by Kirchhoff’s laws. Working characteristic curve is investigated basing on the Multisim simulation. The impacts of power frequency and loads for the critical point are studied. It is shown that the power utilization of the novel pick-up is highly improved about 58.2% by the compensating inductance when working at the critical point. In the end, a prototype system is made and gives a verification of the theoretical analysis and simulation results.At the transmitter of MCR-WPT system, a novel D Boost active power factor corrector is designed, using DSP to realize the control algorithm. A novel D Boost topology is proposed. The MOSFET in conventional D Boost topology is replaced by an IGBT, and two auxiliary diodes are added. As a results, the common mode interference is reduced, and the input current detect is simplified. Then large and small signal analysis are implemented. A precise transfer equation id() is derived for this topology. It is found the simplified transfer equation agrees well with the precise one in the high frequency region. Furthermore, a new duty cycle prediction algorithm with reduced computation cost is proposed to improve the response speeds of the current and input voltage in comparison with the classical average-current-algorithm. An equation of the duty cycle prediction algorithm is derived based on a simple equivalent of the novel D Boost topology. Finally, an APFC converter prototype based on the novel D Boost topology and the duty cycle prediction algorithm is designed. It is shown that the power factor may reach 0.996 and the efficiency is 93.2% at the full load operation mode.