Shared Multi-Channel Cache Design And Memory Architecture Modeling And Verification Based On CPN

Due to the design of low complexity, high performance, low power consumption and other characteristics, Chip Multi-Processors (CMP) becomes the mainstream processor architecture. But the highly integrated on-chip brings tremendous pressure to the high speed concurrent access of each core. CMP is still facing great challenges on the structural design and application development and the design of CMP memory architecture occupies an extremely important position. CMP memory architecture not only can alleviate velocity difference between processor and main memory and affect the security and reliability of data, and also have a huge effect on the multi-core communication.In order to improve the parallelism of data access and provide faster path for data storage and transmission, a kind of Shared multi-channel Cache for CMP architecture utilizing multi-channel Cache (AUMCC) has been proposed.In this thesis, the architecture has been specifically designed, it includes the mapping mechanism design, the Cache coherence protocols design for the storage architecture and the processing mechanism design for concurrent access conflicts of shared multi-channel Cache. The system is analyzed theoretically in improving parallelism in data storage and transmission, improving the efficiency of the multi-core communication and the advantage of simplifying overhead of consistency maintenance. Then CPN hierarchical model is established for AUMCC which based on fully-associative (FA-AUMCC). Thereafter to use CPN Tools to verify and simulate the model’s feasibility and correctness. Meanwhile the verification and the simulation could prove that the system can be realized.