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Research On The Technology Of Array Detector Sub-array Division And Parallel Outputs

Posted on:2015-03-11Degree:MasterType:Thesis
Country:ChinaCandidate:S H YangFull Text:PDF
GTID:2268330428981667Subject:Optical Engineering
Abstract/Summary:PDF Full Text Request
With the development of science and technology innovation, Plane array detector, as one of the core components of modern optical Imaging systems, determines the optical imaging system performance in large extent in recent years.The development of modern science and technology requires optical imaging system work on the dynamic object. In order to acquire high-quality dynamic image, spatial and temporal resolution need to be improved continuously. The main way to improve the spatial resolution is to increase the number of area array detector pixel, and improving time resolution requires high transmission rate of signal or reduce the number of output pixels. To better adapt to the trend of modern optical imaging technology, this paper presents the idea of division, introduces the concept of parallel output, aiming at improving output efficiency with out destroying the hardware devices, and solve the data output problems successfully.Charge-couple device (CCD) compared with CMOS image sensor with wide spectral response, large dynamic range, high sensitivity and fast charge transfer efficiency advantages, therefore, CCD detectors are widely used in the focal plane of the imaging spectrometer.The key technology of the detector is the design of drive timing circuit. Europe and America and other developed countries already have some experience in the design and successful preceden for the development of CCD drive timing circuits, In China, related technologies is still relatively weak. Therefore, the CCD drive timing circuit research and development, master the core technology of the related fields in this country has important strategic significance. While achieving high frame CCD charge signal output, it successful soluted the large amount of data processing and transmission of multispectral, hyper spectral imaging spectrometer.This paper introduces the concept of parallel outputs, the CCD focal plane is divided into two, each output signal is independent, dual parallel outputs, independently of each other, the output signal of the CCD output with two-way, which improve the frame rate of the output signal.First, this paper introduces the working principle and performance indicator of CCD, choose an electronic shutter line transfer type (KAI-0340) as a probe to study, and gives the design method for driving the timing circuit.Finally, use Prote199schematic and PCB design diagram, and produced a circuit board, through debugging the circuit board, drive signal generated by the timing circuit to meet the requirements (KAI-0340) work properly. Summary the design of the drive timing circuit, analysis insufficient and provide the direction for further research.
Keywords/Search Tags:area CCD, Interline transfer, driving timing sequence, FPGA
PDF Full Text Request
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