Digital Part Of A Low-power UHF RFID Tag With Grain Cipher

For its cheap price and user-friendly application, RFID has developed rapidly in recent years.Compared with low-frequency and high-frequency tags, UHF(ultra high frequency) tags has alonger operation range. This feature draws many attentions. However, this feature may also leadto more security problem, because the data spread in air is more easily to steal.Based on the procotol of EPC C1G2, this paper designs a baseband processer of a passiveUHF RFID tag with Grain cipher added.In the beginning, this paper introduces the background and development of RFID andciphers. The algorithm and security of Grain cipher is presented to explain the reason why Graincipher is chosen to protect the data.In the following part, the detail information of EPC C1G2isfocused. In the meantime, self-defined function including memory initialization and Grain cipheris added.Then this paper lists several low-power and low-area motheds which are used in this design.The whole baseband is devided into some modules according to the functions of registers, and itis programed with Verilog HDL. The function of each register, as well as clock input, ispresented, and extra instruction is added to complex combination logic.After coding, this paper runs simulation and FPGA verification to ensure that this design isavailible. Power comsumption and Area usage is estimated at the end. Before place and route, thepower consumption of the processor is11.2μ w calculated by Design Compiler at1.62V supplyvoltage with SMIC18library. The cell area is0.039mm2, and total area is0.353mm2. The powercomsumption and area is relatively low.