Research On Hardware Optimization Implementation And Application Of AES Algorithm

With the fast development of computing technology and network, computers and communication network are used more and more widely in normal life. Online information interchange has become the main access for people to acquire information, and importance of information security has been revalued. Cryptology, which offers the key theory and technology, is irreplaceable in information security. AES is easy to be implemented in hardware and transplanted. Moreover it has a good anti-attacking capability and a high encryption speed. So AES is widely researched and high-performance AES has become the research focus in information security.To avoid the risk caused by probable dropdoor of abroad AES products, independent intellectual property in AES is very necessary. So this paper focuses on design of high-performance AES implementation for network application. The concrete content is as follow:Combinatorial logic of composite field and reuse technology are used in SubBytes and InvSubBytes to reduce the area and resources; reuse technology is used in MixColumns and InvMixColumns.Round unit is divided into seven stages pipelining, and AES hardware implementations of full loop-unrolling and loop iteration of feedback mode are made; the scheme of full loop-unrolling has a relatively high working frequency while the scheme of loop iteration has a better throughout area ratio.In key expansion, composite field algorithm and seven stages pipelining are used to avoid the reduction in throughout and offer real-time encryption roundkeys.Based on message authentication, researches on security protocol for electronic commerce transaction system and hardware design of corresponding terminals are made. The design is able to realize high-speed data authentication, encryption and decryption, digital signature and integrity detection.