Study Of Low-voltage Junctionless IZO Thin Film Transistors

Recently, Oxide Thin Film Transistors （TFT） have been extensivelyinvestigated because of their low process temperature, high mobility and excellenttransmittance, which make them to be valuable in panel displa ys, electronic papersand biosensing technology. However, in relevant literatures, the high operatingvoltage is the problem of oxide TFT, blocking their application in the low voltageand low power electrical devices. This is because traditional TFT gated by thermallygrown SiO₂have low permittivity, causing small capacitance of gate dielectric andhigh operating voltage. Therefore, the key point of reducing device voltage isincreasing capacitance of gate dielectric. Presently, solid electrolyte is the b estchoice of dielectric material because the inner electrons of solid electrolyte canmove to the interface of dielectric, forming electric double layer （EDL） capacitor.The theoretical thickness of EDL capacitor is1nm, making the EDL capacitor havehuge capacitance. The other problem of oxide TFT is complicated fabricationprocesses. The fabrication of oxide TFT require multiple steps of deposition, evensophisticated photoetching when necessary.In our paper，these are targeted researches focusing on solving TFTs problemsabout low operating voltage and novel structure: One is fabricating of mesoporousSiO₂inorganic solid electrolyte as the TFT’s gate dielectric and interpreting the EDLeffect in solid electrolyte. Two is adopting new technique to fabricate oxide channellayers and apply to novel TFT. Our work can be summarized as follows:1. It is reported that mesoporous SiO₂inorganic solid electrolytes weredeposited by plasma enhanced chemical vapor deposition （PECVD） technology atroom temperature. By analysis of scanning electronic microscope, the inner of SiO₂dielectric shows column structure and the tiny holes exist between the columns. TheC-f result indicates that mesoporous SiO₂shows a large capacitance （>1μF/cm²）though their thickness is2μm. In our paper, the EDL-effect theory is proposed andconfirmed by relevant experiments for interpreting this abnormal physicalphenomenon. The finding of mesoporous SiO₂inorganic solid electro lyte andcorresponding EDL theory make direct contribution to next work for TFT of novelstructure. 2. We have successfully fabricated the low-voltage juntionless IZO TFTemployed by mesoporous SiO₂solid electrolyte as gate dielectric and IZO thin filmsas source/drain electrodes and channel layers by one-step mask method. The deviceshows ultra-low operating voltage of2.0V as well as the great device performancewith a current on-off ratio more than10⁶, a subthreshold swing less than120mv/decade. We find that the juntionless device can gradually enhance field-effectregulating and change the operating mode from depletion-mode to enhanced-mode,with the channel thickness decreasing from30nm to10nm.3. In further study, we find that the IZO low-voltage junctionless TFT’sthreshold voltage drifts from negative to positive, leading the device fromdepletion-mode to enhanced-mode by controlling the oxygen flow-rate in sputteringIZO thin-film. Compared with TFT fabricated without oxygen, the TFT fabricate dwith oxygen maintains great performance and stability. Therefore，it is hopeful thatthe low-voltage junctionless TFT based on IZO channel layers would be applied inlow-power and low-cost electrical products.4. Based on the basis, we have successfully fabricated the low-voltagejuntionless TFT with dual in-plane gate. All of the source, drain, channel and gatecan be realized by on-shadow mask on same plane. The device shows ultra-lowoperating voltage of1.0V as well as great performance with small subthresholdswing of75mv/decade, and a large current on-off ratio of4.1×10⁵. According to theresult, we find that the working mechanism of electrostatic gating of in-plane gatecan be analyzed and interpreted by the in-plane gate’s serial-capacitor couplingmodel. Therefore, the low-voltage juntionless TFT with dual in-plane gate can beanalyzed by electrostatic coupling model of three capacitors, which quantitativelyexplains the device’s working mechanism. In addition, the device has logicalfunction employed by in-plane gate as signal input and the output source/draincurrent as signal output, which realizes AND logic. The low-voltage juntionless TFTwith dual in-plane gate will provide a new opportunity for designing low-powerlogic electronic device.