Research On Key Technologies Of Automatic Generation Of Hardware Code For Cryptographic Application

Cryptographic applications are the base of information security, which also are oneof the most important application areas of the FPGA. With the rapid development ofinformation technologies, the system security is confronting several great challengesabout cipher applications, such as the huge data to be encrypted in real time, the threatof hack on Internet. FPGAs can offer the flexibility of software-like and the highperformance of hardware-like. Therefore, it is considered as a better platform foraccelerating cryptographic applications by unitilizing the high speed and stronganti-attack capability. However, there are some problems to implement thecryptographic applications on FPGAs, such as the difficulties of programming, thecomplexities of design pattern and the obstacles of module reuse. The high-levelsynthesis tries to solve these problems above. It can raise the abstraction level of thesystem, simplify the hardware development process and shorten the design cycle.After analyzing the cipher applications, this paper studies several key techniques ofautomatical generation of the hardware code.Firstly, a high-level synthesis framework is proposed for cipher application. Itautomatically generates efficient Verilog code from visual programming language for agiven system platform. The framework is based on the encryption algorithm modulelibrary, in which the modules are pipelined.Secondly, this paper studies the intermediate representation of high-level synthesis,and proposes a two layers graph of hierarchical task graph (HTG) and data flow graph(DFG) based on the module library. Visual Programming Language is converted toHTG by syntax parsing; and the DFG is generated by data renaming. Then the resourcebinding process is performed on the intermediate representation layer, including thebinding of loop module, condition module and synchronization module.Thirdly, this paper studies the implementation of Hash algorithm based on FPGAin order to design efficient encryption algorithm modules. An array structure isproposed using pipeline and parallel technologies. The experiments of MD5and SHA1show that the array structure can achieve a high throughput.Finally, this paper implements the SoPC-based target system to run the hardwarecode, and the hardware code generator to generate the Verilog code from intermediaterepresentation. The experiment on Altera’s Stratix IV GX development boardilluminates that automatically generated hardware code can reach a high speedup.