The Research Of Algorithm In High Level Synthesis Optimization

The design complexity and system function of electronic system have been increasing largely , the competition from the global also shorten the design period , therefore ,the demand for the tools of electronic design automatic is tremendous and the requirement for efficiency of EDA tools is more and more precise . All of this promotes the updating of the electronic design methods and tools in some cases.In this paper we put forward two kinds of high level synthesis method based on researching the technology adopted in other HLS or HLS optimization. One is a specific HLS for control intensive designs, we adopt control-flow graph as the internal representation and use the speculation technology during the scheduling. It is efficient when applied in the control intensive design but the quality of synthesis" results is not well accepted when used for other type of design.The other is a multi-target HLS optimization method, used before the subtask of HLS scheduling .The essence of the method is a system partition algorithm, the multi-target optimization is reflected when convert the behavioral description into a graph. The purpose of the partition is to find the explicit control relation and parallel computation . The internal representation we adopted is a Petri net based one, the partition algorithm is a simulated-annealing algorithm. The method is extensible, that is to say the designers can produce and add their own optimization purpose to the method.We implement the simulated-annealing algorithm and use it to partition the graph gained from the user design .At last, we introduce and illustrate the software part, including the graph input style, the data structure of the result, the method to create candidate result and the cost of result, we also give some experiment data.