Clock Restruction And Optimization Considering The Commonpath

With the development of chip technology entering the deep submicron stage, theimpacts of the process variety and environmental parameters variety on thesemiconductor device delay are becoming increasingly prominent which causes theuncertainty of clock skew that makes timing convergence in very large scale integratedcircuits a key problem. The traditional CTS and ECO methodology cannot fully meetthe requirements of timing convergence. So how to effectively reduce the impact onclock skew generated by PEPV has significant meanings for converging the timing ofthe design. The paper uses a method of increasing clock common path of the relatedtiming unit to reduce the influence of PEPV. The paper puts forward three kinds oftiming optimization methods based on increasing clock common path for the two stagesof before CTS and after CTS.The paper proposes a clock restructuring algorithm for pre-CTS stage. Thealgorithm abstractly models the circuit structure, redistricts the clock sub-tree inmulti-clock gating design using Fiduccia_Mattheyses heuristic algorithm, clusterstiming related units to sub-tree as much as possible and guides the tool to synthesize theclock tree. The experiment result shows that the method can reduce the non-commonpath of the associated timing unit which achieves the purpose of reducing the impact ofPEPV. Compared with before and after clock restructuring, the timing of the design hasbeen improved by39.4%on the whole and the number of violated paths has beenreduced by29.8%.The paper proposes an ECO method of a clock reconstruction for postCTS stage.Under the model of MMMC, the method selects those violated paths that are difficult toconvergence in all cornors caused by skew and it changes the clock structure of thetarget timing paths by increasing the common part of their clock path to reduce the skew.The experiment results show the method successfully reduces the impact of PEPV.This paper proposes a useful skew algorithm considering the common clock path.In the process of implementing useful skew, the algorithm inserts the drivers in thecommon clock paths as much as possible and determines the driver type by look-uptable method. The experiment result shows that the chip performance by applyingproposed algorithm has been improved by3.9%compared with current EDA tools’ flowand it has little impact on design density compared with the fixed delay method.In a word, the paper successfully reduce the clock skew caused by the PEPVoptimizing the timing of the design; besides, the paper reduces iteration cycle, theinsertion number of the optimizing unit, density and power consumption.