Design Of Multi-channel Dual-frequency Digital Receiver Based On FPGA

Digital receiver is a key part of the radar system. Its performance directly affectsthe performance of the whole system. Meanwhile, with the developing of digital signalprocessing theory and microelectronics technology using FPGA design digital receiversystem to become a reality.This paper focuses on the design of multi-channel dual-frequency digital receiver.Using Xilinx Virtex-6FPGA implements the digital down conversion processing of8channels sampled signals. Each sampled signal corresponds to two independent digitaldown conversion channels to achieve dual-channel processing. Then processed signalsare transported to TigerSHARC ADSP TS201S for subsequent signal processing.Design is based on software-defined radio (SDR). Digital local oscillator frequency,decimation ratio, filter coefficients can be controlled by DSP to meet different needs.Digital receiver is modular design Including AD-Interface-Module, DDC-Module,DSP-Interface-Module. Purpose of each module is designed as a generic module toeasily be extended.In this paper digital down conversion (DDC) algorithm implementations is givenbased on software radio (SDR) theory and simulation algorithm on Matlab program.This paper also designs the DDC module on the Xilinx Virtex-6FPGA.AD-Interface-Module and DSP-Interface-Module are designed in order to communicatewith ADC and DSP. Xilinx ISE13.3is used to implement the design. Modelsim SE10.0C is used to simulation. Finally we download the design to the FPGA chip fordebugging and design proved to be correct.