Research Of Memory Race Recording Mechanism In Deterministic Multi-Core Replay Based On SPARC Architecture

Nowadays, with the continuous advancement of electronic and informationtechnology, the people’s demand for high-performance computers is growing moreand more stronger. Limited by the development of material, processor manufacturing,power consumption, heat dissipation and some other reasons, the processor designpattern of increasing the frequency of CPU to increase the processor performance hasencountered difficulties. Integrating the cores onto a single integrated circuit die hasbecome the development of processor design pattern. However, at the same time, italso brought a number of new problems. While having not been arisen in singleprocessor system, the nondeterministic multi-core processor system caused bymemory race is one of the new problems, and this problem is becoming one of thehot areas of computer multi-core structure and parallel computing.The existing multi-core cache coherence protocols in shared memory multi-coreprocessor system can effectively prevent the data inconsistency during programexecuting, but the order of access between multiple threads is out of control. That is,if a multi-thread program executing in a shared memory multi-core processor systemand does not take strict synchronization measures, it may cause the bugs of theviolation of expected program execution sequences. That is, under the circumstanceof repeatedly executions, even if the same inputs may cause the different outputs. Tosolve this problem, the technique of deterministic multi-core replay has beenproposed, and this would ensure the outputs will be the same.Based on the understanding of the SPARC architecture, cache coherenceprotocols and aiming at solving the problems of the nondeterministic shared memorymulti-core processor system of SPARC architecture in CMP architecture, this paperdescribes a memory race recording method in deterministic multi-core replay basedon SPARC architecture——ERTR method. The ERTR method uses the idea ofsliding window and segmenting the instructions into episodes to reduce the log ofmemory race. That is, firstly reduce the redundancy of memory race sequences bymeans of segmenting the instructions of different threads in different processor coresand then reduce the memory race sequence by means of drawing the idea of slidingwindow which is originally in RTR method, that is why this method can reduce thelog of memory race more efficiently. Finally we build a SIMICS+GEMS simulationtest platform with creating a quad-core UltraSPARC processor virtual machine. Thetest programs running in virtual machine are SPLASH-2multithreaded on chip-multiprocessors benchmark suites. Through comparison testing with other memoryrace recording methods on different aspects such as logging space, time cost bandwidth cost, the ERTR memory race recording method has been provedeffectively and efficiently.