Analysis Of The Avalanche Energy For DMOS Fabricated By Trench Filling

In the applications of DMOS devices, the devices failure under UnclampedInductive Switching (UIS) condition is the most important mode. The maximum energyof avalanche in single pulse (EAS)or in repetitive pulse is an important parameter tomeasure the UIS characteristics of DMOS devices. The improvement of DMOSdevices’ EAScan improve its reliability under UIS condition. Therefore, researchingDMOS devices’ EASis very significant. The relationship between the on-resistance inunit area Ron and the breakdown voltage VBof the CB-layer is Ron∝VB1.3, while thatof the conventional voltage sustaining layer is Ron∝VB2.5, which represents abreakthrough to the conventional voltage sustaining layer. It’s the ideal power switchingdevices in the field of power electronics. Based on this, this paper focuses on study theEASof super junction DMOS devices and the methods of improving EAS. The maincontent of this paper is as follows:Firstly, the basic theory of super junction and the UIS related theory were studied.Including super junction structure, working principle, the principle of avalanche energytest and the UIS failure mechanism of super junction DMOS. Use the theory of DMOSdevices to research the affect of parasitic capacitance and during turn-off process onsuper junction DMOS devices. Analyze the UIS failure mechanism of super junctionDMOS devices. Propose the methods to increase the EAS, concerning process, layoutand novel devices.Secondly, design the structure and layout of the super junction VDMOS devices.According to the actual process, make a choice of a reasonable process. The TCADsoftware TSUPREM4and MEDICI were used to simulate and optimize the devicestructure. Use the TCAD software LEDIT to finish the layout of the super junctionVDMOS. Test the static characteristics, the dynamic characteristics and EASof samples.The results of first taping out, show that, the BV is much higher than650V, but the EASis below5.30mJ. Thereafter, employ some methods including the process and layout toimprove the EAS, and re-design, tape out again. Test the samples of second taping out,the results show their EASis2086mJ. EAShas been greatly improved. At last, analyze the super junction VDMOS device with an optimized avalanchecurrent path in detail. Introduce the structure of the novel super junction VDMOS, themechanism of how it improve the UIS characteristics. Use MEDIC to simulate andanalyze the breakdown characteristics and UIS characteristics of the novel superjunction VDMOS. Simulation results show that the EASof the novel super junctionVDMOS increased by39%.