The Reserch And Implementation Of Bit Synchronization Algorithm In TDD Digital Receiver System Based On FPGA

In wireless digital communication systems, one of the key issues for receiving iswhether the signal is sampled and adjudged in the ‘best time’ to improve thetransmission correctness. Receiver synchronization types into frame synchronization,carrier synchronization and bit synchronization, which bit synchronization basis. In acommunication system, in addition to channel noise, inter-code interference is anotherbig interference from transmission process. So channel equalization technology isusually used in receiver.This thesis describes the bit synchronization and equalization algorithm design in awireless digital communication system of the TDD (Time Division Duplex)transmission mode, which has a sampling rate of240MHz, a switching rate of8KHzand a transmission symbol rate of60MHz. The algorithm is based on FPGA+DSP’shardware frame. I design and actualize the bit synchronization algorithm andequalization algorithm function module, as well as the overall state machine and the ADinput data processing module in the slave sink of the two communication sink.At first, this thesis detailedly describes the derivation process of Gardnersynchronization algorithm, then structures the Gardner-bit synchronization algorithmfloating-point simulation model by using Simulink. With the help of a new tool, SystemGenerator, after converted to fixed-point simulation model, hardware code is generatedto make Board Test. Continuous improving the delay structure and parameters of thealgorithm module settings under the guidance of a large number of computer simulationand actual hardware test results (including the baseband environment and the RFenvironment), ultimately a stable and correct FPGA circuit board TDD transceiverfunction is implemented.Bassbang blind equalization algorithm is chosen by author to implement on FPGAas the same design and test way of bit synchronization and the necessity and correctnessis confirmed by testing in RF wireless channel environment. Two algorithms module as the core, the thesis also designs and implements theoverall state machine of the TDD slave sink and the AD input data processing module,including data path switch based on the transfer protocol and an error recoverymechanism adapted to the slave one.After the two TDD communication systems completed, a series of tests includingunidirectional, bidirectional, loopback，IF and RF environment have been finished. Theresults are so good that it shows the success of the design and implementation of the bitsynchronization and equalization algorithm in this thesis.