Research Of Strained MOS Based On The Thin Virtual Substrate

With the development of the integrated circuit, the size of device is getting smallerand smaller, and integrated circuits are becoming more integrated. High-speeddevelopment of integrated circuits promotes the progress of semiconductor industry. Atthe same time, the semiconductor industry is facing the problems of material and devicedimensions. Strained material can greatly improve the mobility of the charge carriersbecause of its special energy band structure, a smaller effective mass and lowerscattering rate. Therefore the use of strained material in the device is an effectivemethod to improve the performance of the devices.The introducing of strain includes two types: global strain and local strain. Peoplepay more attention to global strain, because it has larger strain, no size restrictions, andcan be able to be controlled by varying the content of Ge. The major factor indetermining the global strain is the preparation of virtual substrate. The stress of thestrained Si is determined by the Ge content and the relaxation of virtual substrate, thehigher Ge content and relaxation induced the higher stress. Due to the critical thickness,we need to epitaxial very thick virtual substrate, which would reduce the performance ofdevice.For these problems, production methods of ultra-thin SiGe virtual substrate isdesigned and trial-produced through researching the SiGe layer relaxation mechanismof virtual substrate. And MOS device simulation in the virtual substrate is performedwith device simulation tools.The relaxation mechanism of the epi-SiGe films on a Si substrate is discussed.Stress relaxation model is introduced from the view of dislocation mismatch. Andfinally the testing characterization techniques of virtual substrate material is given.The preparation method of200nm ultra-thin SiGe virtual substrate is designed andtrial-produced, based on the research of dislocations and relaxation mechanism and thecomparison with the other method of preparing a virtual substrate. The results are testedby XRD and Raman. The relaxtion of the ultra-thin SiGe virtual substrate is66.4121%.MOS structures of source heterojunction on ultra-thin SiGe virtual substrate are designed. Device simulation tool is used to simulate the Id-Vdcharacteristic andtransconductance characteristic of the device. It is found that the Gm of SHOT isimprved by90%and33%than the Si NMOS and nomal strained Si NMOS,respectively. And the reasons why the performance of device can be enhanced areanalysed.