Research And Implementation Of Turbo Encoding And Its Parallel Decoding In LTE-A System

Nowadays, the3rd generation mobile communication system has been widelyapplied all around the world. But with the innovation of science and technology, peopleput forward higher requirements. Therefore, based on years of technical reserves andresearch,3GPP drew up Long Term Evolution (LTE) and further made it toLTE-Advanced (LTE-A). The performance of LTE-A far exceeds the requirements ofthe4th generation systems defined by ITU. Accordingly, LTE-A has been identified asthe next-generation standard for mobile communication system, and has been widelysupported by the world’s major telecommunication equipment manufacturers.According to the LTE-A standard protocol, the data channels of the physical layeruse Turbo codes as the channel coding scheme. Turbo codes have superior performanceand can guarantee the reliability of data transmission. However, due to the complexityof Turbo decoding, it brings huge system delay in hardware implementation. Therefore,in order to reach the high data transmission rate in LTE-A, people research on theimprovement for Turbo decoding process and use parallel decoding structure when it isnecessary.In this paper, we first study the Turbo codes, especially its encoding method inLTE-A. On the basis of theoretical analysis, an easily implemented encodingarchitecture in FPGA is proposed. And the final results show that the design in thispaper can encode correctly and fully support all the Turbo encoding length required inLTE-A standard protocols. Simultaneously, the design occupies just a few hardwareresources and gets a very high clock frequency.As for Turbo decoding, this paper studies several decoding algorithms, includingMAP algorithms and SOVA algorithm, then simulates and compares the LOG-MAPalgorithm and Max-LOG-MAP algorithm. The performance of Max-LOG-MAPalgorithm is slightly decreased, but it has a low computational complexity. Therefore,Max-LOG-MAP algorithm is used in the design and implementation of Turbo decoderin this paper. For the parallel processing of Turbo decoding, this paper studies the existingparallel methods, particularly the parallel process of algorithm level. By the MATLABsimulation, it verifies the decoding performance of Max-LOG-MAP algorithm underdifferent degrees of parallelism. In the design of Turbo decoder architecture as well asthe main modules, a structure with8parallelism degree is used. And the implementationresults show that the design can obtain a good decoding performance, while thehardware resources are controlled in a reasonable range. In this paper, theimplementation is carried out on device of Xilinx Kintex-7xc7k325t.