Design Of Missile-Borne Radar Signal Processing System Based On SoPC

Traditional implementation of radar signal processing based on FPGA and DSP can’t meet the design requirements of smaller size, less weight and low power in Missile-Borne Radar Signal Processor. So it is necessary to adopt a new design platform in order to improve the degree of integration in radar signal processing. Using System on Program Chip to complete the radar signal processing with Single FPGA brings several advantages, on the one hand, the real-time performance and reliability of radar system are reserved. On the others hand, the system volume is reduced and the degree of integration are improved. What’s more, the costs are lowered as well. At the same time, Nios Ⅱ is included in the system as a microprocessor, which makes the chip meet the requirements of universal property and multi-mode, modularized, reconfiguration and be programmable.The main contents of this paper consist of analyzing the procedure of radar signal processing and implementing SoPC design with single FPGA. First, Nios Ⅱ microprocessor and design principles of SOPC are introduced in the paper. Then an innovative design solution is given based on SOPC in Missile-Borne system, including hardware and software architecture, workflow, the realization of multi-mode configuration, hardware and software co-design. Finally radar signal processing module are analyzed in detail, including pulse compression, MTD, in order to complete the verification of missile-borne radar signal processing system based on SoPC. The logic design and simulation of radar signal processor based on SOPC is implemented in advanced FPGA. At the same time a method of Spelling Range Profile of Targets based on stepped-frequency radar is given and simulated through measured data.