Design Of The Self-adjusted Bipolar Reference Circuit D/A Converter

The readout circuits of MEMS capacitive accelerometers translate the capacitancevariation into electrical signal. For the balance of the force, DAC is needed to provide astable bias voltage to eliminate the influence of gravitational acceleration. This work issupported by National Science and Technology Major Project of the Ministry of Scienceand Technology of China (20112x05008-005-04-02). In this project, the supply voltageof the DAC is5V and-5V; the reference voltage of the DAC is3.7V and-3.7V; the DNLof the DAC should be less than0.5LSB, the INL of the DAC should be less than2LSB.This thesis describes a general introduction on the development of DAC, and theDAC principle and structures. According to the demand of the project, a10bitcapacitive, resistive DAC and a12bit dual resistor array DAC were designed.A self-adjusted reference circuit was put forward to get higher accuracy and betterlinearity performance in contract to the traditional way. Meanwhile, the resistors of theDAC were used as feedback resistors in this circuit. The die area was reduced by thisway. This circuit is used in the design of the two different DAC structure in this thesis.In the design of the capacitive, resistive DAC, the influence of the mismatch of thecapacitors and resistors to the accuracy was analyzed. And the bit of the MSB and the bitof the LSB was determined by this way. A unique common centroid layout is used in thecapacitor network to reduce the thermal effect or process linear gradients.In the design of the12bit folded resistor-string DAC, the size of the resistors whichhave a direct influence to the performance of the system was discussed. In the design ofthe operate amplifier, the noise was reduced by the certain method. The class AB outputstage was used in the design of output buffer for the demand of the settling time.The test results of the10bit DAC are as follows, in the first tape out, the maximumdifferential nonlinearity (DNL) of the DAC is0.50LSB, the maximum integralnonlinearity (INL) is0.82LSB; in the second tape out, the DNL is0.43LSB, the INL is0.54LSB. It can be seen from the test results that the proposed DAC can meet theengineering requirements well. The post simulation of the12bit folded resistor-stringDAC shows that it meets the demands well.