Study Of System-Level Model For Heterogeneous Multi-core SoC System

Multi-core technology which has the capacity of highly parallel computing andexecuting has become a new way to improve system performance, besidesinstruction-level parallelism and thread-level parallelism. Due to the highly parallelcommunication capabilities, network on chip (NoC) has become one of the mostpopular interconnect communication mechanisms in the chip design of multi-coreeven many-core systems. There are kinds of core types on the chip ofheterogeneous multi-core system, thus it faces with the challenges of highcomplexities to design the architecture and optimize communication mechanisms.Therefore, it’s essential to set up a system-level model to make performanceanalysis and verification for architecture and communication in the early stage ofthe design. This paper focuses on the problem of system-level modeling forarchitecture and on-chip communication in multi-core systems. A variety ofprecision system-level models have been set up. The models can make quantitativeanalysis of the communication performance under different system structures, andprovide reference models for hardware design. The work has the following aspects:1. Designing a cycle-accurate model of network-on-chip. The PCC router andthe wormhole router with virtual channels, which are both cycle-accurate, aredesigned respectively with C++language, and the design of their appropriateresource network interface (RNI) is also completed. Then, a cycle-accurate modelof network-on-chip is set up after the design of on-chip interconnection.2. The evaluation and analysis of the communication performance in thenetwork with different routing structures. PCC network and virtual–channelwormhole routing network, the scale of which is both8×8, have been set uprespectively. The average packet delay and average throughput of them arecompared in the strategy that the communication tasks are distributed randomly.The result of the experiments shows that the average packet delay of the twonetworks is reduced with the increase of packet length, and that of PCC networkhas a greater decrease. It indicates that the PCC network is suitable fortransmission with long packets.3. The evaluation and analysis of the communication performance in thesparse PCC network. Resource nodes are distributed sparsely in the PCC network, and it can provide more transmission links to ease the congestion of PCC network.Compared the average packet delay of16×16sparse PCC network with that of8×8PCC network, it shows that the sparse PCC network can effectively improve thecommunication performance of the network.4. The evaluation and analysis of the communication performance in thenetwork with mixed hierarchical structure. The mixed hierarchical on-chip networkhas been set up, the structure of which is that the outer layer is2D-Mesh and theinner layer is shared-bus. The characteristic parameter of communication is3α inthe normal distribution, and the amount of communication tasks that are mapped onthe physical network is decided by the hops from the source. The result of theexperiments shows that on-chip network with hybrid hierarchical structure issuitable for the application that the frequency of communication is more in localand less in global.5. System integration between network on chip and JPEG decoding. Thesystem-level model of JPEG decoding is completed respectively in pin accurate andmemory accurate. JPEG decoding is decomposed in parallel, and mapped to thePCC network. The system model integrated by network on chip and JPEG decodingcan fulfill parallel decoding of JPEG images.