Research And Implementation Of The FC-AE Protocol Chip Function Coverage Testing Technology

Report on the International Technology Roadmap for Semiconductors in2011points out that the chip design and manufacturing business has entered the “post Moore”era. The increasingly complex functions of integrated chips result in greater difficulty inthe verification of the completeness of chip functions. As an indicator for thecompleteness of functional verification, the importance of functional coverage isself-evident. People have never stopped the research on the functional coverage testtechnology and carried out various research and made achievements from verificationmethodology to the formation of random excitation. However, all these achievementshave different scope of applications and no relatively speedy testing methods have beenfound for the simulated functions of chips provided for in the bus protocol whichrequire more judgments at the present stage.By targeting at the characteristics of the chips in the protocol, this paper advances amethod for the formation of random excitation, which will not only improve theconvergence rate of functional coverage of this type of chip in the process of simulationtesting but also is free from compiling the constraint file for random excitation and thuslargely increases the efficiency of verification.The research and analysis in this paper mainly include the following aspects.Firstly, analyzes the structure of the targeted design, i.e. chips in the air busprotocol, especially the framework for realizing the chip’s internal storage,configuration mode of control register and the characteristics of command frame. Byanalyzing this chip, fetches the key information to be randomized during verification,and works out the verification strategy according to the specifications of chip and setsup the functions to be tested.Secondly, according to the characteristic of more judgments on work pattern fromthe chips in the bus protocol, analyzes all the conditional and judgment statements in thecode, and analyzes and summarizes the probability of occurrence of the implementationresults under various conditions, on the basis of which, studies the relation between thelogical depth of the function points set in the chip function testing in the codes and the number of function points covered by the test vector. Based on research results, thispaper puts forward a method for setting the function point weights and a calculationmethod for testing the excitation adaptability and advances, by combining the geneticalgorithm, a new method for creating random excitation driven by functional coverage.Thirdly, sets up the VMM verification platform according to the verificationstrategy for chips provided for in the air bus protocol and fulfills the verification of theconstrained random excitation function which is generally used among counterparts andthe aforesaid verification of random excitation function based on genetic algorithm onthis platform.Fourthly, verifies the functions of the two methods for creating random excitationand analyzes the code coverage and functional coverage of chips undergoing differentexcitation testing, especially the verification efficiency of functional coverage and thecompleteness of verification. Moreover, this paper also analyses and explains thefunctions of the aforesaid method for creating random excitation during the verificationof functional coverage for chips provided for in the bus protocol and draws a conclusionaccordingly.