The Circuit Design And Realizion Of Cache And MMU Based On ARM9

One of the problems to design the micro-processor is that the limited ofmemory-on-chip fails to meet the increasing demand. Usually, designers would adoptexternal memories with large volume to solve the problem mentioned above. However,the high frequency of micro-processor and the read speed of low rate memories are notin the same order of magnitude. It will limit the performance and efficiencies of themicro-processor. In modern micro-processor, multi-level memory hierarchy hasbecome an effective solution to narrow the memory gap. That is to say, a one-level ortwo-level cache needs to be inserted to make micro-processor’s visit to low ratememories less frequent. Therefore, designing a cache with high performance is crucialto improve the performance and efficiency for the micro-processor.With the rapid development of embedded products, the requirements forembedded equipment are increasingly higher. In modern micro-processor, not only asole program, but also a complicated embedded operation system need to be run, suchas Linux、Windows CE、Android, etc. These multi-task operating system needs thesupport from MMU in process switching and address space protection. We can see thatMMU also remains as the core of modern micro-processor design.This thesis is about to solve the problem mentioned above by regarding ARM9soft core as the research object and designing a cache and MMU which are compatiblewith the core. First of all, the system structure, working principles and involvedalgorithm are aimed to analyze the influence of parameter. After adequateconsideration to the environment of utilizing, chip area and power consumption, allparameter and circuit structure are defined and designing scheme is made. It isfollowed by detailed introduction to the process of circuit design by top-downdesigning method. Finally, module simulation, SW/HW co-simulation, synthesis andSTA are brought to success and prototype verification is completed on FPGA.The experiment result demonstrates the validity of the cache and MMU and theperformance of memory increase of2.11.